JPS5854137U - Binary conversion circuit - Google Patents
Binary conversion circuitInfo
- Publication number
- JPS5854137U JPS5854137U JP14725281U JP14725281U JPS5854137U JP S5854137 U JPS5854137 U JP S5854137U JP 14725281 U JP14725281 U JP 14725281U JP 14725281 U JP14725281 U JP 14725281U JP S5854137 U JPS5854137 U JP S5854137U
- Authority
- JP
- Japan
- Prior art keywords
- binary
- output
- switching transistors
- conversion circuit
- binary conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の機能を示すブロック図、第２図は本考
案の一実施例を示す回路図である。
１：入力端子、２：出力端子、３：＋Ｂ端子、４：アー
ス端子、５：抵抗、６：ＮＰＮトランジスタ、７：抵抗
、８：ＮＰＮトランジスタ、９〜１２：抵抗、１３゜１
４：ダイオード、１５：抵抗、１６：ダイオードミ１７
．１８：抵抗、１９：ＮＰＮトランジスタ、２０゜２１
：ダイオード、２２：抵抗、２３． ２４：ダイオード
。FIG. 1 is a block diagram showing the functions of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1: Input terminal, 2: Output terminal, 3: +B terminal, 4: Earth terminal, 5: Resistor, 6: NPN transistor, 7: Resistor, 8: NPN transistor, 9 to 12: Resistor, 13°1
4: Diode, 15: Resistor, 16: Diode semi-17
．． 18: Resistor, 19: NPN transistor, 20°21
: Diode, 22: Resistor, 23. 24: Diode.
Claims (1)
回路であって、上記２本の２進入力線と各ベース端子が
各々接続された２個あスイッチングトランジスタを併設
し、該２個のスイッチングトランジスタの客コレクタ端
子を２本の２進出力線と各々接続しまた該２個のスイッ
チングトランジスタの各コレクタ端子電圧をＡＮＤ加算
した信号を他の１本の２進出力線とすると共に該ＡＮＤ
加算した信号出力で他のスイッチングトランジスタを制
御しこの制御出力で該２個のスイッチングトランジスタ
の各コレクタ端子出力を制御する如く構成したことを特
徴とする２進変換回路。This circuit obtains three independent binary output signal numbers from two binary input lines, and includes two switching transistors whose base terminals are connected to the two binary input lines, respectively. The collector terminals of the two switching transistors are connected to two binary output lines, and a signal obtained by ANDing the respective collector terminal voltages of the two switching transistors is connected to the other binary output line. and the AND
A binary conversion circuit characterized in that the added signal output controls another switching transistor, and the control output controls each collector terminal output of the two switching transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14725281U JPS5854137U (en) | 1981-10-05 | 1981-10-05 | Binary conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14725281U JPS5854137U (en) | 1981-10-05 | 1981-10-05 | Binary conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5854137U true JPS5854137U (en) | 1983-04-13 |
Family
ID=29940122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14725281U Pending JPS5854137U (en) | 1981-10-05 | 1981-10-05 | Binary conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5854137U (en) |
-
1981
- 1981-10-05 JP JP14725281U patent/JPS5854137U/en active Pending
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