JPS58186610U - Muting circuit - Google Patents

Muting circuit

Info

Publication number
JPS58186610U
JPS58186610U JP8413482U JP8413482U JPS58186610U JP S58186610 U JPS58186610 U JP S58186610U JP 8413482 U JP8413482 U JP 8413482U JP 8413482 U JP8413482 U JP 8413482U JP S58186610 U JPS58186610 U JP S58186610U
Authority
JP
Japan
Prior art keywords
circuit
muting circuit
muting
transistor
grounded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8413482U
Other languages
Japanese (ja)
Inventor
前田 龍国
Original Assignee
クラリオン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クラリオン株式会社 filed Critical クラリオン株式会社
Priority to JP8413482U priority Critical patent/JPS58186610U/en
Publication of JPS58186610U publication Critical patent/JPS58186610U/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)
  • Noise Elimination (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のミューティング回路の回路図、第2図は
本考案によるミューティング回路の回路図である。 1・・・信号ライン入力、2・・・信号ライン出力、3
・・・ミューティング信号出力端子、Q工e Q21 
Q3・・・トランジスタ、Dl・・・ダイオード、R□
・・・抵抗、C□・・・コンデンサ。
FIG. 1 is a circuit diagram of a conventional muting circuit, and FIG. 2 is a circuit diagram of a muting circuit according to the present invention. 1...Signal line input, 2...Signal line output, 3
・・・Muting signal output terminal, Q engineering e Q21
Q3...Transistor, Dl...Diode, R□
...Resistance, C□...Capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 信号ラインがトランジスタを介して接地され、ミューテ
ィング信号出力端子が上記トランジスタのベースに接続
されているミューティング回路において、上記ベースが
抵抗とコンデンサの直列回路を通じて接地されているこ
とを特徴とするミューティング回路。
A muting circuit in which a signal line is grounded through a transistor and a muting signal output terminal is connected to a base of the transistor, wherein the base is grounded through a series circuit of a resistor and a capacitor. ting circuit.
JP8413482U 1982-06-08 1982-06-08 Muting circuit Pending JPS58186610U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8413482U JPS58186610U (en) 1982-06-08 1982-06-08 Muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8413482U JPS58186610U (en) 1982-06-08 1982-06-08 Muting circuit

Publications (1)

Publication Number Publication Date
JPS58186610U true JPS58186610U (en) 1983-12-12

Family

ID=30093100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8413482U Pending JPS58186610U (en) 1982-06-08 1982-06-08 Muting circuit

Country Status (1)

Country Link
JP (1) JPS58186610U (en)

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