JPH021964U - - Google Patents
Info
- Publication number
- JPH021964U JPH021964U JP7999388U JP7999388U JPH021964U JP H021964 U JPH021964 U JP H021964U JP 7999388 U JP7999388 U JP 7999388U JP 7999388 U JP7999388 U JP 7999388U JP H021964 U JPH021964 U JP H021964U
- Authority
- JP
- Japan
- Prior art keywords
- printer
- image signal
- output timing
- delayed
- signal sent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Dot-Matrix Printers And Others (AREA)
- Laser Beam Printer (AREA)
- Exposure Or Original Feeding In Electrophotography (AREA)
- Fax Reproducing Arrangements (AREA)
Description
第１図は本考案の一実施例の構成を示した図、
第２図は第１図の回路の動作説明図、第３図は従
来におけるプリンタの同期制御装回路の信号タイ
ムチヤートを示した図である。
１……クロツク発生器、２……フリツプ・フロ
ツプ、３，４……デイレイライン、８……ＰＬＡ
、９，１０……セレクタ。
FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is an explanatory diagram of the operation of the circuit of FIG. 1, and FIG. 3 is a diagram showing a signal time chart of a conventional synchronization control circuit of a printer. 1...Clock generator, 2...Flip-flop, 3, 4...Delay line, 8...PLA
, 9, 10...Selector.
Claims (1)
ームデイテクト信号と、このプリンタに送る画像
信号の出力タイミングとの同期を制御するプリン
タの同期制御回路において、 前記画像信号の出力タイミングを与えるドツト
クロツクを、このクロツクの周期の１／ｎ（ｎは
正の整数）ずつ遅延させた複数の遅延クロツクを
発生する遅延手段と、 前記ビームデイテクト信号の発生時に、所定の
論理により、前記遅延クロツクの中の１つを選択
し画像信号のドツトクロツクとして出力する選択
手段、 を具備したことを特徴とするプリンタの同期制
御回路。[Claims for Utility Model Registration] In a synchronization control circuit of a printer that controls synchronization between a beam detect signal sent from a laser beam printer and the output timing of an image signal sent to this printer, delay means for generating a plurality of delay clocks in which a dot clock that provides output timing is delayed by 1/n of the period of this clock (n is a positive integer); , a selection means for selecting one of the delayed clocks and outputting it as a dot clock of an image signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7999388U JPH021964U (en) | 1988-06-16 | 1988-06-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7999388U JPH021964U (en) | 1988-06-16 | 1988-06-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH021964U true JPH021964U (en) | 1990-01-09 |
Family
ID=31304840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7999388U Pending JPH021964U (en) | 1988-06-16 | 1988-06-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH021964U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000198235A (en) * | 1998-09-29 | 2000-07-18 | Konica Corp | Clock generator |
-
1988
- 1988-06-16 JP JP7999388U patent/JPH021964U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000198235A (en) * | 1998-09-29 | 2000-07-18 | Konica Corp | Clock generator |
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