JPH01179639U

JPH01179639U -

Info

Publication number: JPH01179639U
Application number: JP7621988U
Authority: JP
Priority date: 1988-06-07
Filing date: 1988-06-07
Publication date: 1989-12-22

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例のブロツク図、第２
図ａ及びｂは第１図の遷移時間帯タイミング生成
回路及び遅延回路の回路図、第３図は本考案の一
応用例のブロツク図、第４図は第３図のブロツク
の動作を説明するためのカウンタ値の状態遷移図
、第５図は第３図のブロツクの動作を説明するた
めの各部の信号タイミング図、第６図は従来のカ
ウンタ論理回路の一例のブロツク図、第７図は第
６図のブロツク図の一応用例のブロツク図、第８
図は第７図のブロツクの動作を説明するための信
号タイミング図である。１……カウンタ論理回路、１８……遷移時間帯
タイミング生成回路、１９……カウント実行回路
、２４……遅延回路、ＣＬＫ……クロツク信号、
……クリア信号、Ｄａ〜Ｄｄ……初期値信
号、Ｅ……カウント状態遷移時間帯信号、……
ストローブ信号、Ｑａ〜Ｑｄ……カウンタ出力信
号、Ｓｒ_１……遅延クロツク信号、Ｓ_ｒ２……遅
延ストローブ信号、Ｓｒ_３……遅延クリア信号、
τ……カウント信号遷移時間帯。 Figure 1 is a block diagram of one embodiment of the present invention;
Figures a and b are circuit diagrams of the transition period timing generation circuit and delay circuit in Figure 1, Figure 3 is a block diagram of an example of application of the present invention, and Figure 4 is for explaining the operation of the block in Figure 3. 5 is a signal timing diagram of each part to explain the operation of the block in FIG. 3, FIG. 6 is a block diagram of an example of a conventional counter logic circuit, and FIG. Block diagram of one application example of the block diagram in Figure 6, No. 8
This figure is a signal timing diagram for explaining the operation of the block in FIG. 7. 1... Counter logic circuit, 18... Transition time period timing generation circuit, 19... Count execution circuit, 24... Delay circuit, CLK... Clock signal,
... Clear signal, Da to Dd ... Initial value signal, E ... Count state transition time period signal, ...
Strobe signal, Qa to Qd...counter output signal, _Sr1 ...delayed clock signal, _Sr2 ...delayed strobe signal, _Sr3 ...delayed clear signal,
τ...Count signal transition time period.

Claims

[Scope of utility model registration request]

A counter logic circuit having a counter execution circuit that inputs an enable signal, a clear signal, a clock signal, and a strobe signal and outputs an n-ary counter signal (n is a natural number). 1. A counter logic circuit comprising a transition time period timing generation circuit which inputs a strobe signal and outputs a NOR signal of each delayed signal as a count transition time signal.