JPS62183233U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of this invention, FIGS. 2 a to f are time charts for explaining the operation of the same embodiment, and FIG. 3 shows the configuration of a conventional timing signal generator. Block diagram shown, No. 4
Figures a and b are time charts for explaining the operation of this timing signal generator. In the figure, 1 is a clock generator, 2a is a first
2b is a second counter, 3 is a pattern generation memory, 4 is a flip-flop, and 5 is a pattern periodic control memory. In each figure, the same reference numerals indicate the same or corresponding parts.

Amendment December 25, 1981 The scope of claims for utility model registration is amended as follows.

[Claims for Utility Model Registration] A first counter and a second counter for counting clocks, and storing information regarding the period, and counting the second counter by specifying an address using the count output of the first counter. a first memory that outputs a control signal; and a second memory that stores random pattern information and outputs a random pattern by addressing with the count output of the second counter; A label output from the second memory according to the information.
1. A timing signal generating device that determines a repetition period of a random pattern.

Claims (1)

[Scope of utility model registration request] a first counter and a second counter that count clocks; and a first counter that stores information regarding the period and outputs a count control signal for the second counter by addressing with the count output of the first counter. a second memory that stores random pattern information and outputs the random pattern by addressing with the count output of the second counter; A timing signal generator characterized in that the repetition period of a random pattern output from a memory is determined.