KR890005988A - Monostable multi-circuit by pulse accumulation - Google Patents

Monostable multi-circuit by pulse accumulation Download PDF

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Publication number
KR890005988A
KR890005988A KR870009876A KR870009876A KR890005988A KR 890005988 A KR890005988 A KR 890005988A KR 870009876 A KR870009876 A KR 870009876A KR 870009876 A KR870009876 A KR 870009876A KR 890005988 A KR890005988 A KR 890005988A
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KR
South Korea
Prior art keywords
circuit
terminal
counter
pulse accumulation
monostable multi
Prior art date
Application number
KR870009876A
Other languages
Korean (ko)
Inventor
이영준
한광수
Original Assignee
유인영
대한전선 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 유인영, 대한전선 주식회사 filed Critical 유인영
Priority to KR870009876A priority Critical patent/KR890005988A/en
Publication of KR890005988A publication Critical patent/KR890005988A/en

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Abstract

내용 없음No content

Description

펄스누적에 의한 단안정 멀티회로Monostable multi-circuit by pulse accumulation

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 회로도,1 is a circuit diagram of the present invention,

제3도는 제1도의 각 단자점 출력파형도.3 is an output waveform diagram of each terminal point of FIG.

Claims (1)

입력신호(a)를 인가시켜서 된 카운트(CT1)를 이용한 단안정 멀티회로에 있어서, 카운터(CT1)의 출력단자(A)에서 콘덴서(C1)를 거쳐 외부 콘트롤신호(b)와 같이 저항 (R1)과 인버터(IN1)(IN2)를 구성한 래치회로(LH)를 통해서 발진기(OSC)에 인가시키는 동시에 카운터(CT2)의 클리어단자(CL)에 인가되도록 연결하고, 발진기(OSC)의 출력(F)을 클럭단자(CK)에 입력시킨 카운터(CT2)의 임의 펄스 설정의 출력단자(H)를 갖게하고, n+1의 출력단자(I)는 다이오드(D1) 거쳐 래치회로(LH)의 입력단자(B)에 연결하여서 된 것을 특징으로 하는 펄스 누적에 따른 단안정 멀티회로.The input signal (a) the as applied by the count (CT 1) a monostable in the multi-circuit, the counter (CT 1) the output terminal (A) Capacitor (C 1) to the external control signal via (b) in the using The oscillator is connected to the oscillator OSC through the latch circuit LH constituting the resistor R 1 and the inverter IN 1 and IN 2 , and to be applied to the clear terminal CL of the counter CT 2 . The output terminal H of the arbitrary pulse setting of the counter CT 2 which inputs the output F of the (OSC) to the clock terminal CK, and the output terminal I of n + 1 is the diode D 1. A monostable multi-circuit according to the pulse accumulation, characterized in that connected to the input terminal (B) of the latch circuit (LH) through. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed based on the initial application.
KR870009876A 1987-09-07 1987-09-07 Monostable multi-circuit by pulse accumulation KR890005988A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR870009876A KR890005988A (en) 1987-09-07 1987-09-07 Monostable multi-circuit by pulse accumulation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR870009876A KR890005988A (en) 1987-09-07 1987-09-07 Monostable multi-circuit by pulse accumulation

Publications (1)

Publication Number Publication Date
KR890005988A true KR890005988A (en) 1989-05-18

Family

ID=68343845

Family Applications (1)

Application Number Title Priority Date Filing Date
KR870009876A KR890005988A (en) 1987-09-07 1987-09-07 Monostable multi-circuit by pulse accumulation

Country Status (1)

Country Link
KR (1) KR890005988A (en)

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