JPS59118326U - N-stage reset type M-series generation circuit - Google Patents
N-stage reset type M-series generation circuitInfo
- Publication number
- JPS59118326U JPS59118326U JP882383U JP882383U JPS59118326U JP S59118326 U JPS59118326 U JP S59118326U JP 882383 U JP882383 U JP 882383U JP 882383 U JP882383 U JP 882383U JP S59118326 U JPS59118326 U JP S59118326U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- generation circuit
- value
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のＮ段すセット形Ｍ系列発生回路を示す回
路図、第２図は本考案によるＮｆｉリセット形Ｍ系列発
生回路の実施例を示す回路図である。
１．２，３，４，５，６．７・・・フリップフロップ、
６′・・・遅延素子、８・・・排他的論理和回路。FIG. 1 is a circuit diagram showing a conventional N-stage set type M-sequence generation circuit, and FIG. 2 is a circuit diagram showing an embodiment of the Nfi reset type M-sequence generation circuit according to the present invention. 1.2, 3, 4, 5, 6.7... flip-flop,
6'...Delay element, 8...Exclusive OR circuit.
Claims (1)
フリップフロップの出力および中段のフリップフロップ
の出力を排他的論理和回路の入力に接続し、その出力を
初段のフリップフロップの入力に接続してなるＮ段すセ
ット形Ｍ系列発生回路において、リセット時点で所定の
リセット値と所定のＭ系列の値が等しいフリップフロッ
プであって、その保持する値が当該フリップフロップに
リセットをかけなかった際に取りうるＭ系列の初期値の
如何にかかわらず常に所定のＭ系列を発生せしめるリセ
ット値に等しい値をとるレリツプフロルプを、当該フリ
ップフロップと同じ遅延時間を有する遅延素子に置換し
て構成したことを特徴とするＮ段すセット形Ｍ系列発生
回路。N flip-flops are connected in cascade, the output of the final stage flip-flop and the output of the middle stage flip-flop are connected to the input of an exclusive OR circuit, and the output is connected to the input of the first stage flip-flop. In an N-stage set type M-sequence generation circuit, when a predetermined reset value and a predetermined M-sequence value are equal at the time of reset, and the value held by the flip-flop is The flip-flop is constructed by replacing a flip-flop which takes a value equal to a reset value that always generates a predetermined M-sequence regardless of the initial value of the M-sequence to be generated, with a delay element having the same delay time as the flip-flop. N-stage set type M-series generation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP882383U JPS59118326U (en) | 1983-01-25 | 1983-01-25 | N-stage reset type M-series generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP882383U JPS59118326U (en) | 1983-01-25 | 1983-01-25 | N-stage reset type M-series generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59118326U true JPS59118326U (en) | 1984-08-09 |
Family
ID=30140303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP882383U Pending JPS59118326U (en) | 1983-01-25 | 1983-01-25 | N-stage reset type M-series generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59118326U (en) |
-
1983
- 1983-01-25 JP JP882383U patent/JPS59118326U/en active Pending
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