JPS58129744U - T flip-flop circuit with priority circuit - Google Patents

T flip-flop circuit with priority circuit

Info

Publication number
JPS58129744U
JPS58129744U JP2436382U JP2436382U JPS58129744U JP S58129744 U JPS58129744 U JP S58129744U JP 2436382 U JP2436382 U JP 2436382U JP 2436382 U JP2436382 U JP 2436382U JP S58129744 U JPS58129744 U JP S58129744U
Authority
JP
Japan
Prior art keywords
circuit
flip
priority
trigger
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2436382U
Other languages
Japanese (ja)
Other versions
JPH036034Y2 (en
Inventor
司 西野
Original Assignee
日本コロムビア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本コロムビア株式会社 filed Critical 日本コロムビア株式会社
Priority to JP2436382U priority Critical patent/JPS58129744U/en
Publication of JPS58129744U publication Critical patent/JPS58129744U/en
Application granted granted Critical
Publication of JPH036034Y2 publication Critical patent/JPH036034Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例を示す回路図、第２図は本考案の一実施
例を示す回路図である。 図中、５けフリップフロップ、９はナンド回路、１０は
トリガ回路である。FIG. 1 is a circuit diagram showing a conventional example, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. In the figure, 5 flip-flops, 9 a NAND circuit, and 10 a trigger circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号パルスの到来毎に反転する１７９７１７０７１
回路と、電源投入直後にトリガパルスを発生するトリガ
回路と、上記１７９７１７０７１回路の出力が所定レベ
ルであるときに上記トリガパルスを上記１７９７１７０
７１回路の入力側に加算するゲート回路とからなること
を特徴とする優先回路を有する１７９７１７０７１回路
。179717071 inverted every time an input signal pulse arrives
a trigger circuit that generates a trigger pulse immediately after power is turned on; and a trigger circuit that generates a trigger pulse when the output of the 179717071 circuit is at a predetermined level.
179717071 circuit having a priority circuit characterized by comprising a gate circuit that adds to the input side of the 71 circuit.
JP2436382U 1982-02-23 1982-02-23 T flip-flop circuit with priority circuit Granted JPS58129744U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2436382U JPS58129744U (en) 1982-02-23 1982-02-23 T flip-flop circuit with priority circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2436382U JPS58129744U (en) 1982-02-23 1982-02-23 T flip-flop circuit with priority circuit

Publications (2)

Publication Number Publication Date
JPS58129744U true JPS58129744U (en) 1983-09-02
JPH036034Y2 JPH036034Y2 (en) 1991-02-15

Family

ID=30036368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2436382U Granted JPS58129744U (en) 1982-02-23 1982-02-23 T flip-flop circuit with priority circuit

Country Status (1)

Country Link
JP (1) JPS58129744U (en)

Also Published As

Publication number Publication date
JPH036034Y2 (en) 1991-02-15

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