JPS5952763U - Control clock pulse and dial pulse generator - Google Patents

Control clock pulse and dial pulse generator

Info

Publication number
JPS5952763U
JPS5952763U JP14590882U JP14590882U JPS5952763U JP S5952763 U JPS5952763 U JP S5952763U JP 14590882 U JP14590882 U JP 14590882U JP 14590882 U JP14590882 U JP 14590882U JP S5952763 U JPS5952763 U JP S5952763U
Authority
JP
Japan
Prior art keywords
pulse
dial
control clock
pulses
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14590882U
Other languages
Japanese (ja)
Inventor
茂樹 大和
Original Assignee
株式会社宮川製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社宮川製作所 filed Critical 株式会社宮川製作所
Priority to JP14590882U priority Critical patent/JPS5952763U/en
Publication of JPS5952763U publication Critical patent/JPS5952763U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案の一実施例を示す回路図である。 ＤＴＥ・・・データ端末装置、ＥＣＭ・・・電子計算機
、ＭＯＤＥＭ・・・変復調装置、ＣＯＮ・・・０及びＣ
ＵＮ−１・・・周波数カウンター、Ｆ１〜Ｆ、。・・・
フリップフロップ、Ｇ１・・・アンドゲート、Ｇ２・・
・ナントゲート、ＣＯＭＰ・・・比較回路、Ｅ、　ＡＰ
、　Ｐ、　Ｓ及びＣＭ・・・リレー、ＣＵＮ−２〜ＣＵ
Ｎ・・・５・・・計数回路。The drawing is a circuit diagram showing an embodiment of the present invention. DTE...data terminal equipment, ECM...electronic computer, MODEM...modulation/demodulation equipment, CON...0 and C
UN-1...Frequency counter, F1 to F. ...
Flip-flop, G1...and gate, G2...
・Nant gate, COMP...comparison circuit, E, AP
, P, S and CM...Relay, CUN-2~CU
N...5...Counting circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 所要パルス周期より充分短い周期の正確なパルスを発生
する一つの時刻パルス発生回路を設け、その出力を２進
分周手段で多数回分周して各種時限回路用のクロックパ
ルスを得るとともに前記分周段の複数の出力をジャンパ
ーの接続またはジャンパープラグにより組み合わせてリ
セット・セット・フリップフロップのセット・リセット
信号とし、そのフリップフロップの出力により所要の速
度及びメーク・ブレーク比をもつ交換機制御用アナログ
ダイヤルパルスを発生させることを特徴とする制御用ク
ロックパルスおよびダイヤルパルス発生装置。One time pulse generation circuit that generates accurate pulses with a period sufficiently shorter than the required pulse period is provided, and its output is frequency-divided many times by a binary frequency dividing means to obtain clock pulses for various time-limiting circuits. The multiple outputs of the stages are combined by jumper connections or jumper plugs to create reset/set/flip-flop set/reset signals, and the output of the flip-flops is used to generate analog dial pulses for controlling the exchange with the required speed and make/break ratio. A control clock pulse and dial pulse generator, characterized in that it generates a control clock pulse and a dial pulse.
JP14590882U 1982-09-27 1982-09-27 Control clock pulse and dial pulse generator Pending JPS5952763U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14590882U JPS5952763U (en) 1982-09-27 1982-09-27 Control clock pulse and dial pulse generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14590882U JPS5952763U (en) 1982-09-27 1982-09-27 Control clock pulse and dial pulse generator

Publications (1)

Publication Number Publication Date
JPS5952763U true JPS5952763U (en) 1984-04-06

Family

ID=30324940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14590882U Pending JPS5952763U (en) 1982-09-27 1982-09-27 Control clock pulse and dial pulse generator

Country Status (1)

Country Link
JP (1) JPS5952763U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4732563U (en) * 1971-04-30 1972-12-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4732563U (en) * 1971-04-30 1972-12-12

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