JPH0357629U - - Google Patents

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Publication number
JPH0357629U
JPH0357629U JP11795989U JP11795989U JPH0357629U JP H0357629 U JPH0357629 U JP H0357629U JP 11795989 U JP11795989 U JP 11795989U JP 11795989 U JP11795989 U JP 11795989U JP H0357629 U JPH0357629 U JP H0357629U
Authority
JP
Japan
Prior art keywords
input terminal
flip
pulse
circuit
flop circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11795989U
Other languages
Japanese (ja)
Other versions
JP2524566Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989117959U priority Critical patent/JP2524566Y2/en
Publication of JPH0357629U publication Critical patent/JPH0357629U/ja
Application granted granted Critical
Publication of JP2524566Y2 publication Critical patent/JP2524566Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案によるモノマルチ回路の実施例
を示す回路図、第2図は第1図のタイミングチヤ
ート、第3図は従来のモノマルチ回路の回路図、
第4図は第3図のタイミングチヤート、第5図は
第4図のタイミングチヤートの一部にヒゲ状のパ
ルスが挿入されたタイミングチヤートである。 1……入力端子、2……第1のDフリツプフロ
ツプ回路、3……第1のパルスデイレ回路、4…
…第2のDフリツプフロツプ回路、5……第2の
パルスデイレ回路、6……出力端子、7……入力
信号パルス幅、8……雑音信号パルス幅、9〜1
6……各波形、17……入力端子、18……Dフ
リツプフロツプ回路、19……パルスデイレ回路
、20……出力端子、21〜30……各波形。
FIG. 1 is a circuit diagram showing an embodiment of a monomulti circuit according to the present invention, FIG. 2 is a timing chart of FIG. 1, and FIG. 3 is a circuit diagram of a conventional monomulticircuit.
4 is a timing chart of FIG. 3, and FIG. 5 is a timing chart in which whisker-like pulses are inserted into a part of the timing chart of FIG. 4. DESCRIPTION OF SYMBOLS 1...Input terminal, 2...First D flip-flop circuit, 3...First pulse delay circuit, 4...
...Second D flip-flop circuit, 5...Second pulse delay circuit, 6...Output terminal, 7...Input signal pulse width, 8...Noise signal pulse width, 9-1
6...Each waveform, 17...Input terminal, 18...D flip-flop circuit, 19...Pulse delay circuit, 20...Output terminal, 21-30...Each waveform.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データをクロツク入力端子に入力し、Q出力端
子からのパルスを第1のパルスデイレ回路により
時間だけ遅延させてR入力端子に入力し、デ
ータ入力端子をハイレベルにした第1のDフリツ
プフロツプ回路と、クロツク入力端子を前記第1
のDフリツプフロツプ回路の出力端子に接続す
るとともにデータ入力端子を前記第1のDフリツ
プフロツプ回路のクロツク入力端子に接続し、Q
出力端子からのパルスを第2のパルスデイレ回路
によりT時間だけ遅延させてR入力端子に入力
する第2のDフリツプフロツプ回路とからなり、
前記T時間以上の長さの入力データのみを受け
付けるように構成したことを特徴とするモノマル
チ回路。
A first D flip-flop circuit that inputs data to the clock input terminal, delays the pulse from the Q output terminal by T1 time by the first pulse delay circuit, inputs it to the R input terminal, and sets the data input terminal to a high level. and connect the clock input terminal to the first
the first D flip-flop circuit, and the data input terminal is connected to the clock input terminal of the first D flip-flop circuit;
It consists of a second D flip-flop circuit that delays the pulse from the output terminal by T2 hours by a second pulse delay circuit and inputs the delayed pulse to the R input terminal,
A monomulti circuit, characterized in that it is configured to accept only input data with a length of T1 hours or more.
JP1989117959U 1989-10-09 1989-10-09 Hybrid gas meter and gas pressure regulator Expired - Lifetime JP2524566Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989117959U JP2524566Y2 (en) 1989-10-09 1989-10-09 Hybrid gas meter and gas pressure regulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989117959U JP2524566Y2 (en) 1989-10-09 1989-10-09 Hybrid gas meter and gas pressure regulator

Publications (2)

Publication Number Publication Date
JPH0357629U true JPH0357629U (en) 1991-06-04
JP2524566Y2 JP2524566Y2 (en) 1997-02-05

Family

ID=31666156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989117959U Expired - Lifetime JP2524566Y2 (en) 1989-10-09 1989-10-09 Hybrid gas meter and gas pressure regulator

Country Status (1)

Country Link
JP (1) JP2524566Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62187159A (en) * 1986-02-10 1987-08-15 株式会社村田製作所 Low temperature sinterable ceramic composition for multi-layer substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62187159A (en) * 1986-02-10 1987-08-15 株式会社村田製作所 Low temperature sinterable ceramic composition for multi-layer substrate

Also Published As

Publication number Publication date
JP2524566Y2 (en) 1997-02-05

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