JPH0357629U - - Google Patents
Info
- Publication number
- JPH0357629U JPH0357629U JP11795989U JP11795989U JPH0357629U JP H0357629 U JPH0357629 U JP H0357629U JP 11795989 U JP11795989 U JP 11795989U JP 11795989 U JP11795989 U JP 11795989U JP H0357629 U JPH0357629 U JP H0357629U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- flip
- pulse
- circuit
- flop circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001934 delay Effects 0.000 claims 2
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Measuring Volume Flow (AREA)
Description
第１図は本考案によるモノマルチ回路の実施例
を示す回路図、第２図は第１図のタイミングチヤ
ート、第３図は従来のモノマルチ回路の回路図、
第４図は第３図のタイミングチヤート、第５図は
第４図のタイミングチヤートの一部にヒゲ状のパ
ルスが挿入されたタイミングチヤートである。
１……入力端子、２……第１のＤフリツプフロ
ツプ回路、３……第１のパルスデイレ回路、４…
…第２のＤフリツプフロツプ回路、５……第２の
パルスデイレ回路、６……出力端子、７……入力
信号パルス幅、８……雑音信号パルス幅、９〜１
６……各波形、１７……入力端子、１８……Ｄフ
リツプフロツプ回路、１９……パルスデイレ回路
、２０……出力端子、２１〜３０……各波形。
FIG. 1 is a circuit diagram showing an embodiment of a monomulti circuit according to the present invention, FIG. 2 is a timing chart of FIG. 1, and FIG. 3 is a circuit diagram of a conventional monomulticircuit.
4 is a timing chart of FIG. 3, and FIG. 5 is a timing chart in which whisker-like pulses are inserted into a part of the timing chart of FIG. 4. DESCRIPTION OF SYMBOLS 1...Input terminal, 2...First D flip-flop circuit, 3...First pulse delay circuit, 4...
...Second D flip-flop circuit, 5...Second pulse delay circuit, 6...Output terminal, 7...Input signal pulse width, 8...Noise signal pulse width, 9-1
6...Each waveform, 17...Input terminal, 18...D flip-flop circuit, 19...Pulse delay circuit, 20...Output terminal, 21-30...Each waveform.
Claims (1)
子からのパルスを第１のパルスデイレ回路により
Ｔ１時間だけ遅延させてＲ入力端子に入力し、デ
ータ入力端子をハイレベルにした第１のＤフリツ
プフロツプ回路と、クロツク入力端子を前記第１
のＤフリツプフロツプ回路の出力端子に接続す
るとともにデータ入力端子を前記第１のＤフリツ
プフロツプ回路のクロツク入力端子に接続し、Ｑ
出力端子からのパルスを第２のパルスデイレ回路
によりＴ２時間だけ遅延させてＲ入力端子に入力
する第２のＤフリツプフロツプ回路とからなり、
前記Ｔ１時間以上の長さの入力データのみを受け
付けるように構成したことを特徴とするモノマル
チ回路。 A first D flip-flop circuit that inputs data to the clock input terminal, delays the pulse from the Q output terminal by T1 time by the first pulse delay circuit, inputs it to the R input terminal, and sets the data input terminal to a high level. and connect the clock input terminal to the first
the first D flip-flop circuit, and the data input terminal is connected to the clock input terminal of the first D flip-flop circuit;
It consists of a second D flip-flop circuit that delays the pulse from the output terminal by T2 hours by a second pulse delay circuit and inputs the delayed pulse to the R input terminal,
A monomulti circuit, characterized in that it is configured to accept only input data with a length of T1 hours or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989117959U JP2524566Y2 (en) | 1989-10-09 | 1989-10-09 | Hybrid gas meter and gas pressure regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989117959U JP2524566Y2 (en) | 1989-10-09 | 1989-10-09 | Hybrid gas meter and gas pressure regulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0357629U true JPH0357629U (en) | 1991-06-04 |
| JP2524566Y2 JP2524566Y2 (en) | 1997-02-05 |
Family
ID=31666156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989117959U Expired - Lifetime JP2524566Y2 (en) | 1989-10-09 | 1989-10-09 | Hybrid gas meter and gas pressure regulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2524566Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62187159A (en) * | 1986-02-10 | 1987-08-15 | 株式会社村田製作所 | Low temperature sinterable ceramic composition for multi-layer substrate |
-
1989
- 1989-10-09 JP JP1989117959U patent/JP2524566Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62187159A (en) * | 1986-02-10 | 1987-08-15 | 株式会社村田製作所 | Low temperature sinterable ceramic composition for multi-layer substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2524566Y2 (en) | 1997-02-05 |
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