JPH018059Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a frequency dividing circuit for a composite synchronizing signal, which extracts a frequency-divided signal of a horizontal synchronizing signal from a composite synchronizing signal in which a horizontal synchronizing signal and a vertical synchronizing signal are combined.

BACKGROUND ART A synchronization circuit of a television receiver is configured to separate and amplify a synchronization signal from a composite video signal and apply it to horizontal and vertical deflection circuits. in this case,
An example of a synchronization signal separated from a composite video signal is a composite synchronization signal as shown in FIG. 1A,
The polarity inversion signal of the vertical synchronization signal shown in C of the same figure is superimposed on the horizontal synchronization signal shown in B of the same figure as, for example, an exclusive OR. Therefore, it is necessary to separate the horizontal and vertical synchronization signals from each other before applying the composite synchronization signal to the horizontal and vertical deflection circuits. For this reason, generally, the difference in pulse width between the two synchronizing signals is used to separate the horizontal synchronizing signal using a differentiating circuit and the vertical synchronizing signal using an integrating circuit. FIGS. 1D and 1G illustrate differential and integral outputs obtained when the composite synchronizing signal is passed through a differentiating circuit 2 and an integrating circuit 13, respectively, which will be described later. In this example, since the composite synchronization signal itself is a signal consisting of the exclusive OR of the horizontal synchronization signal and the polarity inverted signal of the vertical synchronization signal, among the differential outputs,
It is unavoidable that the pulse interval is disturbed in the portions corresponding to the leading and trailing edges of the vertical synchronization signal.

By the way, in a receiver in which the deflection circuit and the high-voltage circuit are separated, it is possible, for example, to divide the frequency of the horizontal oscillation pulse supplied to the deflection circuit and supply it to the high-voltage circuit. In this case, for example, as in the frequency divider circuit 1 shown in FIG. 2, a differential output obtained by differentiating a composite synchronizing signal in a differentiating circuit 2 is supplied to a trigger input terminal 3t of a trigger type flip-flop circuit 3, Furthermore, a circuit configured to differentiate the output of the flip-flop circuit 3 again by a differentiating circuit 4 may be used. However, when this type of circuit is used, the disturbance in the pulse interval of the differential output directly appears in the output of the flip-flop circuit 3 as a trigger timing shift, as shown in FIG. 1E. As a result, as shown in FIG. 1F, the output of the differentiating circuit 4, which is a frequency-divided output, is such that the interval between the differential outputs before and after the leading edge of the vertical synchronizing signal is more than twice the length of one horizontal scanning period H. At this time, the phase shift △
There was a drawback that T was not corrected and was affected by the subsequent differential output. That is, the oscillation frequency of the high-voltage circuit is divided with respect to the oscillation frequency of the deflection circuit, leaving a phase shift, which has the drawback of adversely affecting the operation of both circuits and their peripheral circuits.

DISCLOSURE OF THE INVENTION The present invention eliminates the above-mentioned drawbacks, and supplies the differential output obtained by differentiating the composite synchronization signal to the flip-flop circuit, further differentiates and divides the frequency, and adjusts the trigger timing of the flip-flop circuit. It is an object of the present invention to provide a frequency dividing circuit for a composite synchronization signal, which corrects the deviation by a correction circuit that operates by detecting the leading edge of a vertical synchronization signal included in the composite synchronization signal.

In order to achieve this objective, the present invention provides a composite synchronization signal in which a polarity inverted signal of a vertical synchronization signal is superimposed on the horizontal synchronization signal as an exclusive OR,
A differentiating circuit that differentiates this composite synchronization signal, a trigger type flip-flop circuit that is triggered by the differential output of the differentiating outputs of this differentiating circuit, and a trigger type flip-flop circuit that differentiates the output of this flip-flop circuit to 1/1/1 of the differential output. A differentiating circuit that obtains a divided output of a frequency of The gist of the invention is that it is composed of a correction circuit that performs correction.

According to the present invention, in order to obtain a frequency-divided output of half the frequency of the horizontal synchronization signal from a composite synchronization signal in which a polarity inverted signal of the vertical synchronization signal is superimposed on the horizontal synchronization signal as an exclusive OR, The inconvenience that the trigger timing of the flip-flop circuit shifts due to the phase shift of the differential output that occurs at the leading edge of the synchronizing signal can be corrected by using a correction circuit that operates by detecting the leading edge of the vertical synchronizing signal. In that case, the tolerance for errors in the detection timing by the correction circuit is relatively large, and it is not necessary to exactly match the leading edge of the vertical synchronization signal, so a slight detection delay is not a problem. Therefore, there is no need to make the design conditions of the time constant circuit used to separate the vertical synchronization signal very strict, and as a result, it is possible to accurately 1/2 of the horizontal synchronization signal with a simple circuit configuration and without phase shift. It has excellent effects such as being able to divide the frequency by two.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3 and 4. FIG. 3 is a schematic circuit diagram showing an embodiment of a frequency dividing circuit for a composite synchronizing signal according to the present invention, and FIG. 4 is a circuit diagram of the main part thereof.

In FIG. 3, the composite synchronization signal frequency dividing circuit 11 is supplied with a composite synchronization signal obtained by superimposing the polarity inverted signal of the vertical synchronization signal on the horizontal synchronization signal as an exclusive OR, like the frequency division circuit 11, and A differentiating circuit 2 for differentiating, a trigger type flip-flop circuit 3 and a flip-flop circuit whose positive polarity output among the differential outputs of the differentiating circuit 2 is supplied to a trigger input terminal 3t, and which inverts the state each time a positive polarity differential output is input. 3, and has a differentiating circuit 4 for differentiating the output.

Here, the frequency dividing circuit 11 includes the circuits 2, 3,
In addition to circuit 4, a correction circuit 12 is provided. Correction circuit 1
2 constitutes the main part of the present invention, and in the case of this embodiment, an integration circuit 13 is supplied with a composite synchronization signal and integrates it, and an integral output of the integration circuit 13 is supplied and differentiated. Thereafter, the differential circuit 14 is connected to the reset input terminal 3r of the flip-flop circuit 3.

Here, the specific circuit configuration of the correction circuit 12 is as shown in FIG. The integrating circuit 13 includes a transistor Q ₁ which is supplied with a composite synchronization signal as a base and amplifies it to a predetermined signal level, and an emitter follower type transistor connected to the collector of this transistor Q ₁ via a coupling capacitor C ₁ .
_Q2 , and a low frequency time constant circuit 13a consisting of a resistor _R1 and an integrating capacitor _C2 connected to the emitter of the transistor _Q2 . This integrating circuit 13 can extract only the vertical synchronization signal included in the composite synchronization signal. Differential circuit 14
is a capacitor coupling the integral output of the integrating circuit 13.
A transistor Q ₃ is supplied to the base via C ₃ to shape the waveform, a transistor Q ₄ for phase inversion is connected to the collector of this transistor Q ₃ via a resistor R ₂ , and the emitter of this transistor Q ₄ It consists of a high-frequency time constant circuit 14a consisting of a differential capacitor _C4 and a resistor _R3 connected to the circuit, and a clamping diode D connected in parallel to the resistor _R3 of the time constant circuit 14a. This differential circuit 1
4 extracts only the leading edge differential pulse with positive polarity among the differential pulses obtained at the leading edge and trailing edge of the vertical synchronization signal extracted by the integrating circuit 13.

The signal waveforms of each part of the correction circuit 12 described above are as shown in FIGS. 1G and 1H. That is,
As shown in FIG. 1G, the vertical synchronization signal separated from the composite synchronization signal by the integration circuit 13 has a sawtooth uneven waveform because it contains a horizontal synchronization signal component. transistor for
The waveform is shaped at _Q3 to form a rectangular pulse shown by the dotted line in Figure 1H. Therefore, the high-frequency time constant circuit 14a outputs accurate differential pulses at two points, the rising edge and the falling edge of the rectangular pulse, but only the rising differential pulse is extracted by the action of the diode D.

In this way, the correction circuit 12 supplies the differential pulse obtained at the rising edge (leading edge) of the vertical synchronization signal included in the composite synchronization signal to the reset input terminal 3r of the flip-flop circuit 3 as a correction pulse. Here, the state of the flip-flop circuit 3 immediately before this correction pulse is supplied is a set state as shown in FIG. Become.

However, since the correction pulse from the correction circuit 12 is supplied to the reset input terminal 3r of the flip-flop circuit 3, the flip-flop circuit 3 is activated for one horizontal scanning period from the leading edge of the vertical synchronizing signal, as shown in FIG. It is reset before H elapses. Therefore, when this one horizontal scanning period H has elapsed, the flip-flop circuit 3 is set, and the shift in trigger timing seen in the conventional frequency dividing circuit 1 can be prevented. In this embodiment, as shown in FIG. 1J, the flip-flop circuit 3 is
After is reset, the interval between differential pulses will deviate somewhat from 2H until the third differential pulse, but
The period of the subsequent differential pulse is exactly 2H.

In this way, according to the horizontal synchronization signal frequency dividing circuit 11 having the above configuration, a temporary phase difference is obtained from the composite synchronization signal in which the polarity inverted signal of the vertical synchronization signal is superimposed on the horizontal synchronization signal as an exclusive OR. Excluding the shifted portion, it is possible to accurately divide the frequency of the horizontal synchronization signal by half with almost no phase shift.
In addition, when correcting the shift in the trigger timing of the flip-flop circuit 3 that occurs when frequency-dividing the superimposed portion of the vertical synchronization signal by the correction circuit 12 that operates by detecting the leading edge of the vertical synchronization signal, the vertical Even if a detection error occurs due to a delay in the operation of the integrating circuit 13 that detects the leading edge of the synchronizing signal, the next trigger pulse will be detected by the flip-flop circuit 3 from the time of detection.
Since it is only necessary to reset the flip-flop circuit 3 with a correction pulse before the signal is supplied to the circuit, a slight detection error is not a problem, and the design conditions of the time constant circuits 13a, 14a, etc. need not be made stricter. This means that you can get away with it without having to worry about it.

Furthermore, by easily obtaining a frequency-divided output of 1/2 the frequency of the horizontal sync signal included in the composite sync signal, high-voltage circuits such as television receivers can be divided into horizontal oscillation circuits and deflection circuits. It is possible to operate at a low frequency where the ratio is an integer ratio, and thereby the high voltage circuit can be operated stably without causing a lack of dynamic range.

[Brief explanation of the drawing]

1A to 1J are signal waveform diagrams of a composite synchronization signal and various signals obtained by its waveform conversion, respectively; FIG. 2 is a circuit configuration diagram showing an example of a conventional horizontal synchronization signal frequency dividing circuit; FIG. 3 is a circuit configuration diagram showing an embodiment of a frequency dividing circuit for a composite synchronizing signal according to the present invention, and FIG. 4 is a circuit diagram of a main part thereof. 2... Differential circuit, 3... Flip-flop circuit, 3t... Trigger input terminal, 3r... Reset input terminal, 4... Differential circuit, 11... Frequency divider circuit,
12... Correction circuit, 13... Integrating circuit, 14...
Differential circuit.

Claims (1)

[Scope of utility model registration request] A composite synchronization signal in which a polarity inverted signal of a vertical synchronization signal is superimposed on a horizontal synchronization signal as an exclusive OR is supplied, and a differentiation circuit that differentiates the composite synchronization signal and a positive polarity differential of the differential output of the differentiation circuit are supplied. a trigger-type flip-flop circuit that is triggered by the output; a differentiation circuit that differentiates the output of the flip-flop circuit to obtain a frequency-divided output with a frequency of 1/2 of the differential output; A frequency dividing circuit for a composite synchronous signal, comprising a correction circuit that detects a leading edge of a synchronous signal, resets the flip-flop circuit at the time of detection, and corrects a shift in trigger timing of the flip-flop circuit.