JPH0619251Y2 - Synchronous circuit - Google Patents

Description

[Detailed Description of the Invention] [Industrial field of application] The present invention is based on a phase-locked loop (PLL: Phase Lo).
The so-called AFC (Automatic F)
The present invention relates to a synchronizing circuit adapted to perform a requency control operation, and is applied to, for example, a television receiver, a video tape recorder, or the like.

[Outline of device]

INDUSTRIAL APPLICABILITY The present invention uses a flyback pulse as a timing pulse in a synchronizing circuit applied to a television receiver, a video tape recorder or the like to form a ramp-shaped waveform signal in which a center voltage and an average voltage are coincident with each other and used for phase error detection. This stabilizes the AFC operation using the PLL control, enhances the noise resistance, and facilitates the adjustment.

[Conventional technology]

Generally, in television receivers, video tape recorders, and the like, in order to stabilize the synchronization system, a synchronization circuit that performs AFC operation using PLL control is adopted.

Conventionally, in a synchronous circuit using PLL control, a flyback pulse (horizontal pulse) is integrated to form a ramp-shaped waveform signal, and the ramp-shaped signal is sampled at the timing of the synchronous signal to generate an error voltage corresponding to the phase error of AFC. To obtain this error voltage from a voltage controlled oscillator (so-called VC
I tried to give a negative feedback to O). The voltage-controlled oscillator is free-running at the synchronous frequency.

[Problems to be solved by the invention]

By the way, as shown in FIG. 5, the pulse width of the flyback pulse in a television receiver or the like is usually 10 to 20.
Since it is about μsec, the average voltage and the central voltage of the ramp-shaped waveform signal obtained by integrating this are different. When the ramp waveform signal formed by integrating the flyback pulse is used for detecting the phase error in the AFC operation, the response speed of the AFC loop is different because the average voltage and the center voltage of the ramp waveform signal are different. If it is slow, the phase information and frequency information may be confused with each other, resulting in a deadlock state. This narrows the frequency change width of the voltage-controlled oscillator and determines the response time of the loop filter. Cannot be increased, the capture range of the PLL is narrow, and it is easily affected by noise.
Therefore, in the conventional synchronous circuit, the temperature characteristic of the free-running frequency of the voltage controlled oscillator, the fluctuation of the power supply voltage, the adjustment accuracy, and the like must be made strict, and the so-called H-gear is generated against noise. There was a problem that it was easy.

Therefore, in consideration of the above-mentioned conventional problems, the present invention provides a P
(EN) Provided is a synchronizing circuit having a novel configuration in which the capture range of LL is expanded to stabilize AFC operation, noise resistance is enhanced, and adjustment is facilitated.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention forms a pulse having a predetermined width by using a flyback pulse taken out from a flyback transformer as a timing pulse in a synchronous circuit having a phase locked loop for synchronous control. A pulse forming circuit, a waveform shaping circuit for shaping the pulse supplied from the pulse forming circuit into a ramp-shaped waveform signal in which the average voltage and the center voltage match, and a ramp-shaped waveform signal supplied from the waveform shaping circuit. A sample and hold circuit that samples and holds with a sampling pulse formed from a synchronization signal, and the signal level of the hold output of the sample and hold circuit supplied through a filter and the central voltage level of the ramp waveform signal are approximately A level controller that compares the levels of equal reference signal levels and generates an error voltage. And a voltage-controlled oscillator having a free-running frequency equal to the horizontal frequency and having an error voltage obtained by the level comparator supplied as a control voltage, and a ramp-shaped waveform signal corresponding to the flyback pulse. The error voltage corresponding to the level difference between the signal level of the hold output of the sample and hold circuit for the inclined portion and the reference signal level substantially equal to the center voltage level of the ramp-shaped waveform signal is used as a control voltage, and the voltage is negatively fed back to the voltage. It is characterized in that it is configured to control the oscillation phase of the controlled oscillator.

[Action]

In the synchronizing circuit according to the present invention, a ramp-shaped waveform signal in which the average voltage and the center voltage formed by using the flyback pulse as a timing pulse is matched is used for phase error detection, and the center voltage of the ramp-shaped waveform signal is detected. By performing PLL control of the voltage-controlled oscillator having a free-running frequency, a deadlock state is prevented and a stable AFC operation is performed.

〔Example〕

Hereinafter, an embodiment of a synchronizing circuit according to the present invention will be described in detail with reference to the drawings.

The embodiment shown in the block diagram of FIG. 1 is one in which the present invention is applied to a synchronous processing system of a television receiver, in which an oscillation output of a voltage controlled oscillator 1 which is free-running at a horizontal frequency fh is a drive circuit 2. From the transformer 3 through the transformer 3.

Then, the pulse forming circuit 4 includes the transformer 8 to the second
The flyback pulse FBP having the horizontal scanning period Th as shown in FIG.
A pulse P having a duty of 50% is formed as shown in FIG. 2B using BP as a timing pulse. Here, the pulse forming circuit 4 may be configured using, for example, a mono multivibrator. As shown in FIG. 3, the free-running frequency of the voltage controlled oscillator 1 is set to 2N · fh (where N is a positive integer) and the horizontal output is performed via the 1 / 2N frequency divider 10. By using the set-priority RS flip-flop 4A as the pulse forming circuit 4 and by triggering the RS flip-flop 4A with the flyback pulse FBP and horizontal output, a pulse P having a predetermined pulse width is output. Is formed, it is convenient for integrated circuit because it does not require capacitance.

The waveform shaping circuit 5 also shapes the pulse P supplied from the pulse forming circuit 4 into a ramp-shaped waveform signal S as shown in FIG. 2C in which the average voltage Vav and the center voltage Vcn match. In the waveform shaping circuit 5, for example, the pulse P is supplied to one base as shown in FIG.
PN transistors 51 and 52, two PNP transistors 53 and 54 which are switching-controlled reciprocally by the differential pair NPN transistors 51 and 52, and the PN
NP whose switching is controlled by the P transistor 54
It is composed of an N-transistor 55 and an integrating capacitor 56 having a charge path formed through the PNP transistor 53 and a discharge path formed through the NPN transistor 55.

The ramp waveform signal S obtained by the waveform shaping circuit 5 is supplied to the sample and hold circuit 6. The sample-and-hold circuit 6 is supplied with a television signal from a television tuner (not shown) and a horizontal synchronizing signal separated from the television signal by a synchronizing separation circuit 9 as a sampling pulse. To sample and hold the ramp-shaped waveform signal S. The hold output of the sample and hold circuit 6 is supplied to the level comparator 8 via the filter 7, and its signal level Vs is compared with the reference signal level Vref. The reference signal level Vref is
The central voltage Vcn of the ramp-shaped waveform signal S is set to a signal level when sampled and held.

Then, the error voltage obtained by the level comparator 8 is negatively fed back to the voltage controlled oscillator 1 as a control voltage to form a synchronous circuit for performing AFC operation by PLL control.

That is, in the rising slope portion of the ramp-shaped waveform signal S, the ramp-shaped waveform signal S is higher than the reference signal level Vref set to the signal level when the center voltage Vcn of the ramp-shaped waveform signal S is sampled and held. When the signal level of the sample and hold output is lower, that is, when the phase of the flyback pulse FBP is delayed, the oscillation phase of the voltage controlled oscillator 1 is advanced,
Further, when the signal level of the sample hold output of the ramp-shaped waveform signal S is higher than the reference signal level Vref, that is, when the phase of the flyback pulse FBP is advanced, the voltage controlled oscillator 1 Phase control by negative feedback is performed so as to delay the oscillation phase. As a result, the oscillation phase of the voltage controlled oscillator 1 is stabilized in a state in which the central voltage Vcn of the ramp waveform signal S can be sampled and held.

On the other hand, in the falling slope portion of the ramp-shaped waveform signal S, when the signal level of the sample-hold output of the ramp-shaped waveform signal S is lower than the reference signal level Vref, that is, the phase of the flyback pulse FBP. Is advanced, the oscillation phase of the voltage controlled oscillator 1 is advanced, and when the signal level of the sample hold output of the ramp waveform signal S is higher than the reference signal level Vref, that is, the fly When the phase of the back pulse FBP is delayed, it operates so as to delay the oscillation phase of the voltage controlled oscillator 1, so that positive feedback occurs, and a stable state exists at the falling slope portion of the ramp-shaped waveform signal S. do not do. That is, according to the present invention, the stable state is only when sampling is performed by the flyback pulse at the timing of the central voltage of the rising slope portion of the ramp-shaped waveform signal S.

The center voltage Vcn of the falling slope portion of the ramp-shaped signal S is equal to the voltage at the stable point of the PLL loop, but the center voltage Vcn of the falling slope portion is the same.
Even if is sampled and held, the fluctuation due to thermal noise or the like is positively fed back, so that the rising slope portion of the ramp-shaped waveform signal S is sampled and held and the phase is controlled by negative feedback. Will be done. That is, the central voltage Vcn of the falling slope portion of the ramp waveform signal S does not become a stable point of the PLL loop.

In the embodiment having the above-mentioned configuration, the ramp-shaped waveform signal S
When the center voltage Vcn of the signal is sampled and held, the loop control works so that the voltage controlled oscillator 1 oscillates at the horizontal frequency fh, and the horizontal signal added to the television signal supplied to the sync separation circuit 9 is added. It is possible to obtain a horizontal sync output in which the phase is fixed to the sync signal. Moreover,
Since the oscillation frequency of the voltage controlled oscillator 1 in the state where the phase is fixed matches the free-running frequency of the voltage controlled oscillator 1, even if the response speed of the loop is slowed, the PLL is in a deadlock state. Never be. Therefore, the range of frequency change of the voltage controlled oscillator 1 can be widened to expand the capture range, and the time constant of the filter 7 can be increased to make it difficult to be influenced by external noise and to achieve stable AFC operation. You will be able to do it. Further, it becomes unnecessary to make the operating temperature characteristics and the adjustment accuracy of the voltage controlled oscillator 1 too high.

[Effect of device]

As is clear from the above description of the embodiments, in the synchronizing circuit according to the present invention, the ramp-shaped waveform signal in which the average voltage and the central voltage formed by using the flyback pulse as the timing pulse is matched is used for the phase error detection. By controlling the voltage-controlled oscillator, which has a free-running frequency at the center voltage of the ramp-shaped waveform signal, by PLL control, it is possible to prevent a deadlock state, so that the capture range of the PLL is expanded to increase the AFC operation. It is possible to achieve stabilization, enhance noise resistance, and facilitate adjustment.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronizing circuit according to the present invention, FIG. 2 is a timing chart showing the operation of the above embodiment, and FIG. 3 is a main part showing a modification of the above embodiment. FIG. 4 is a block diagram, and FIG. 4 is a circuit diagram showing a specific circuit configuration example of the waveform shaping circuit in the above embodiment. FIG. 5 is a waveform diagram for explaining the problems of the conventional synchronizing circuit. DESCRIPTION OF SYMBOLS 1 ... Voltage controlled oscillator, 3 ... Transformer 4 ... Pulse generator, 5 ... Waveform shaping circuit 6 ... Sample and hold circuit 7 ... Filter 8 ... Level comparator 9 ... Sync separation circuit

Claims (1)

[Scope of utility model registration request] 1. A pulse forming circuit for forming a pulse having a predetermined width by using a flyback pulse taken out from a flyback transformer as a timing pulse in a synchronous circuit having a phase locked loop for synchronous control, and the pulse forming circuit. A waveform shaping circuit that shapes the pulse supplied from the waveform shaping circuit into a ramp-shaped waveform signal in which the average voltage and the center voltage match, and a ramp-shaped waveform signal supplied from the waveform shaping circuit described above into a sampling pulse formed from a synchronization signal. The sample and hold circuit that performs sample and hold is compared with the signal level of the hold output of the sample and hold circuit supplied through the filter and the reference signal level that is approximately equal to the center voltage level of the ramp waveform signal. , A level comparator that generates an error voltage, and a horizontal frequency A voltage-controlled oscillator having a new free-running frequency and to which the error voltage obtained by the level comparator is supplied as a control voltage, and the sample for the ramp portion of the ramp-shaped waveform signal corresponding to the flyback pulse. Feedback control of the oscillation phase of the voltage-controlled oscillator by using the error voltage according to the level difference between the signal level of the hold output of the hold circuit and the reference signal level substantially equal to the center voltage level of the ramp-shaped waveform signal as the control voltage. A synchronous circuit characterized by being configured as follows.