JPS5927129B2 - phase synchronized circuit - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a phase-locked circuit, and in particular, it operates extremely stably against external pulse noise when detecting the synchronization state of a phase-locked loop and expanding the loop pull-in range. It provides the configuration of the circuit.

The phase-locked loop related to this invention includes a voltage-controlled oscillator and a phase comparator that supplies a control signal to the oscillator via a low-pass filter, like the well-known phase-locked loop (PLL) system. However, the phase comparator is configured to generate an error signal according to the phase difference between the input signal and the output signal of the voltage-controlled vibrator, and the synchronous state of this loop is determined by the free-running frequency of the voltage-controlled vibrator. is obtained when the frequency of the input signal is approximately equal to the frequency of the input signal, and in this case, both frequencies match and the phase difference between them is approximately π/2 (rad).

On the other hand, an asynchronous state is likely to occur when the frequencies of the voltage-controlled oscillator and the input signals are different, and when the output beat signal of the phase comparator that occurs in this state is attenuated by a low-pass filter, this loop will no longer be possible. It no longer has the function to return to a synchronized state.

Therefore, in order to recover, it is necessary to take some action to bring the free-running frequency of the voltage-controlled keepsake closer to the frequency of the input signal.

In a receiving device with such a phase-locked loop, it is desirable to be able to automatically remove noise caused by beats that occur in an unsynchronized state, display a synchronized state, and even return to a synchronized state. The detection function of synchronous and asynchronous states is disclosed in patent application No. 51-15462 by the present applicant.
There is one described in the specification of No. 7 "Phase synchronizer".

In this device, a voltage-controlled token 1 as shown in FIG.
A phase-locked loop comprising a first phase comparator 2 which generates a control signal of π/2 (rad
) A second phase comparator 3 (that is, an amplitude synchronized demodulator) that operates on different phase axes is provided, and a rectifier circuit 4 for determining the synchronization state is provided on the output side of this second phase comparator.
It is described that the rectifying polarity is selected to be opposite to the demodulating polarity of the second phase comparator described above.

A phase synchronization device having this type of structure may have drawbacks when applied to a wireless AM receiver, and will be explained below using an example of application to a video detection stage of a television receiver.

For example, when receiving a signal mixed with pulse noise caused by a hair dryer, etc., the signal at the output end of the amplitude synchronous demodulator 3 (second phase comparator), that is, the input end of the rectifier circuit 4, has a zero value. Noise exceeding the carrier wave level is superimposed, and since this rectifier circuit 4 has a so-called amplitude separation type configuration in which it is DC coupled to a video detector, there is a drawback that it operates due to noise even when the phase-locked loop is in a synchronous state.

Therefore, if such a rectifier circuit is used to detect the synchronization state and its output is used to display the synchronization state or to control a circuit for expanding the pull-in range, malfunctions will occur, so it is not suitable for practical use. It is something that will disappear.

The present invention aims to improve the noise resistance of the above-mentioned amplitude-separated phase-locked state detection mechanism, and particularly to provide one with a function for expanding the pull-in range of the phase-locked loop.

In the present invention, a first phase comparator (hereinafter referred to as phase comparator) that constitutes a normal phase-locked loop includes a λ low-pass filter and a voltage-controlled vibrator, and the above-mentioned phase comparator and π
/2 (rad) A second phase comparator (hereinafter referred to as a video detector) configured to operate on a different phase axis, a level comparator DC-coupled to its output terminal, and an output of the level comparator A phase shifter consisting of a first waveform shaping circuit for converting into a substantially sawtooth wave signal, a second waveform shaping circuit for converting its output signal into a substantially rectangular wave signal, and an integrator placed on the output side of the first waveform shaping circuit. A synchronous state detection circuit is arranged.

The present invention has the feature that expanding the pull-in range of the phase-locked loop does not require any special new circuit, and can be achieved simply by setting the charging/discharging time constant ratio of the integrator to a predetermined value.

Embodiments will be described in detail below using drawings showing examples.

FIG. 2 is a block diagram showing the configuration of an embodiment of the phase synchronization circuit according to the present invention.

A phase-locked loop consisting of the voltage-controlled vibrator 1, the phase comparator 2, and the low-pass filter 5 synchronizes the oscillation frequency of the voltage-controlled vibrator with the frequency of the video carrier wave of the input signal at the terminal T1.
In the synchronous state, the phase difference between them is relatively approximately π/
2 (rad), and the video detector 3 is the oscillator 1 described above.
The function of an in-phase synchronous detector is provided by the arrangement of the phase shifter 6 which shifts the phase of the output by π/2 (r a d ).

These arrangements are well known as an example of the configuration of an amplitude locked detector using a phase locked loop.

The level comparator 7 is connected to the video detector 3 as shown in FIG. 3a.
The operation starting point V2 is given so as to detect a signal in a direction exceeding the zero carrier wave level (1) of the output.

Therefore, when the phase-locked loop is in an asynchronous state, a pulse-like signal as already shown in the figure is obtained at the output of the level comparator 7, which corresponds to a half cycle of the beat signal.

Next, when the phase-locked loop is in the synchronized state and receives a signal mixed with pulse-like noise, the level comparator 7
The noise 'vN1 in the detection output signal 8 shown in Figure C is outputted (V'N1) as shown in Figure d.

The operation of the level comparator 7 in this embodiment described above is the same as that in the conventional device, but the stability against noise is significantly improved due to the complexity of the signal processing described below.

First, a first waveform shaping circuit 8 disposed on the output side of the level comparator 7 is configured to generate a sawtooth wave signal only when the level comparator 7 generates a continuous signal with a duplication of approximately 450%. .

For example, such a circuit includes a charging circuit with a predetermined charging time constant, a circuit that detects the charge level of the charging circuit, and a circuit that stops the charging operation of the charging circuit for a predetermined period only, and a discharging circuit. This can be easily achieved by using a wood-throwing wood (details will be described later).

By arranging such a first waveform shaping circuit 8, the waveforms shown in FIG. 3e and f are obtained at its output end for the beat signal and noise.

The waveform shown in FIG. 3e occurs when the phase-locked loop is out of synchronization.

The output beat signal of the level comparator 7 is a continuous pulse signal with a duty of 50% as already shown in the figure, and is charged from the ground (GND) level to the level of V3 at a predetermined time constant, and then reaches the level of ■3. It is shown that when the voltage V4 is reached, the discharge circuit starts operating and discharges the charged charge, and the voltage drops to the level (4).When the voltage reaches the level V4, the discharge operation stops, and thereafter, the charging and discharging operations are repeated.

On the other hand, the noise V'N1 (FIG. 3d) detected when the phase-locked loop is in the synchronized state drives the charging circuit with a time constant greater than or equal to the charging time constant using the aforementioned beat signal.

However, this noise is pulse-like and usually occurs intermittently.

For example, the well-known hair dryer noise is synchronized with the frequency of the commercial power supply with a duty of about 10% or less.

Therefore, the charging peak level of the charging circuit due to such pulse noise is the level shown in Figure 3 f, which is significantly different from the waveform generated by the beat signal, and at this time the discharging circuit remains in a stopped state. continue.

From the above-mentioned points b, an effective signal processing method for the output of the first waveform shaping circuit 8 arranged according to the present invention will be found.

That is, there is a large difference in the DC level of the output of the first waveform shaping circuit between the beat signal and the noise, and the charging detection circuit and the discharging circuit stop operating in response to the noise.

Therefore, the second waveform shaping circuit 9 arranged according to the present invention converts into a rectangular wave by a slice circuit with a slice level near level 3 shown in FIG. This can be realized by configuring it for use.

FIG. 4 shows that the above-described slicing circuit is used in the second waveform shaping circuit 9 to obtain a rectangular wave signal from the input sawtooth wave signal by slicing it at the level of 0.
The rectangular wave signal shown by the solid line in the same figure corresponds accurately only to the beat signal.

As described above, the present invention provides a level comparator and a first and second
The waveform shaping circuit is arranged in a DC-coupled state to the output side of the video detector, and a rectangular wave signal that accurately corresponds to the beat signal that occurs only when the phase-locked loop is in an asynchronous state is generated. This is obtained at the output end of the second waveform shaping circuit, and by integrating it into a waveform as shown by the broken line in FIG. 4, it can be used as a signal for expanding the pull-in range of the phase-locked loop.

FIG. 5 shows the output of the second waveform shaping circuit of the present invention converted into a substantially sawtooth wave by an integrator 10, combined with the output of the low-pass filter 5 of the phase-locked loop, and supplied to the voltage-controlled oscillator. and second
This shows that a phase-locked loop is constructed.

Although there are various factors that determine the locking range of a phase-locked loop, it is a well-known fact that this low-pass filter 5 in particular greatly affects the locking range.
), which is one of the factors that limits its application to the video detection stage of television receivers.

According to the configuration shown in FIG. 5 of the present invention, since it has a second phase-locked loop that sweeps the voltage controlled oscillator using the output of the integrator 10, a wide pull-in range can be achieved depending on the output level of the integrator. You can expand Koki.

In actual application, since the output of the integrator 10 includes a direct current component, it is desirable to have a configuration in which only the outside of the alternating current is superimposed on the low-pass filter 3 via a direct current blocking capacitor.

Next, a description will be given of FIG. 6, which shows a preferred concrete circuit of the first and second waveform shaping circuits I of the phase synchronized circuit of the present invention.

A pair of transistors Q1 whose emitters are commonly connected. Q2 constitutes a level comparator, and the operation start level of this stage is set by the voltage source E1.

Assuming that the signal supplied to the base of transistor Q1 has the polarity shown in FIG.
1 supplies the DC level of ■2 to the base of transistor Q2.

Darlington connected PNP transistor Q3 and NP
N) Transistor Q4 charges integrating capacitor C1 via resistor R1 in accordance with the output of the level comparator.

The transistor is Q5. Q6 and Q7 are for detecting the charge level of the integrating capacitor C1, and are usually
That is, when the charge level of capacitor C1 is low,
Bias resistor R2r so that this detection circuit is turned off
The ratio of R3 is set to a predetermined value.

Resistor R4, which constitutes the discharge circuit, and transistor Q8 (!1-1-A resistor R arranged to switch the base bias of transistor Q,
5. Transistor Q9 also remains off.

This condition will not change unless the charge level of integrating capacitor C1 becomes higher than the base bias level of transistor Q6.

When the phase-locked loop is in lock, the level comparator formed by transistors Ql and Q2 described above will only respond to noise above the zero carrier level (eg, VNl in FIG. 3C).

The duty ratio of such noise is very small and the charge level of the integrating capacitor C7 cannot reach the level of the base bias of the transistor Q6, so the transistor Q5 of the charge detection circuit still remains off and the second integrator No other signal can be obtained at the emitter terminal of the transistor Q9 that constitutes the transistor Q9.

On the other hand, if the phase-locked loop is in an asynchronous state, the level comparator of transistor Qt and Q2 will reliably respond to the component exceeding the zero carrier level of the beat signal, and the level comparator of Qt and Q2 will reliably respond to a signal with a duty of approximately 50% (for example, as shown in Figure 3). ) continues to charge the integrating capacitor C1.

In order to change transistor Q5 from an off state to an on state, the peak level of the voltage at the emitter terminal of transistor Q4 must be higher than the base bias level of transistor q provided by resistors R2 and R3.

Transistor Q5 turns on.Q7, Qs-
All transistors Q9 and QIO enter the on state.

Transistor Q8 starts discharging the charge of integrating capacitor C1 with a time constant limited by resistor R4, but capacitor C1 is still being charged by transistor Q4.

On the other hand, the base bias of transistor Q6 is lowered by the ON operation of transistor Q9.

Therefore, in order to turn off the transistor Q again, the base potential of Q5 needs to become lower than the base potential of Q6, and for this reason, the discharge time constant of resistor R4 and capacitor C1 is It is set to be smaller than the charging time constant due to R1.

As explained above, the on-period of transistor Q5 roughly corresponds to the difference in time constant between charging and discharging of the integrator including capacitor C1, so transistor QI
A signal is obtained at the base of O that produces a positive pulse only while Q5 is on.

This pulse signal is connected to transistor Q and 0% capacitor C2.
, is converted into a substantially sawtooth wave signal by an integrator constituted by a resistor R6, and is used as a sweep signal of the voltage-controlled vibrator.

In the specific configuration shown in FIG. 6 described above, when configuring the integrator in the first waveform shaping circuit, the charging section and the discharging section are configured to operate independently, and this discharging section is controlled by the charging detection circuit. It is arranged so that

Therefore, it has the advantage that there is no need to newly provide the second waveform shaping circuit described in the basic configuration of the present invention, that is, a circuit for converting a sawtooth wave signal into a rectangular wave signal.
In the configuration shown in FIG. 6, the circuit can be modified depending on the application.

For example, it may be selected arbitrarily to provide a load to the collector of the transistor Q6 or to obtain a rectangular wave signal from its base.

Further, in such a specific configuration, a resistor can be connected in parallel to the capacitor C1 in order to further improve stability against noise.

This means that in the configuration shown in FIG. 6, the capacitor C1 charged by noise is transferred to the transistors Q, , Q5.
It is discharged only by the leakage current in the off-state of Qs, and this value in normal silicon transistors is extremely small.

Therefore, there is a practical advantage that the above-described arrangement of the resistors can prevent the transistor Q5 from entering the on state when noise occurs repeatedly.

This invention detects the synchronization and non-synchronization states of the phase-locked loop, and in the non-synchronization state, automatically obtains a signal for expanding the loop pull-in range using an amplitude synchronized detector and a level comparator placed on its output side. A first waveform shaping circuit converts the output into a sawtooth wave signal, a second waveform shaping circuit converts the output into a rectangular wave signal, and an integrator converts this output into a substantially sawtooth wave signal. Although the output has been described as being supplied to a voltage controlled oscillator, it goes without saying that the application is not limited to this type of output.

In particular, the integrator can provide a constant level of DC output by selecting its integration time constant depending on the application.

In this case, this integrator is preferably constructed as a peak value rectifier circuit.

It is also easy to output a plurality of detection signals with different waveforms, and all of these are included in the scope of the present invention.

Needless to say, the advantages brought about by this invention include not only realizing a synchronized state detection operation that does not cause malfunctions due to pulse noise, but also greatly expanding the loop pull-in range by arranging the second phase-locked loop. It is suitable for integrated circuits because all circuits can be configured with DC coupling, and there are fewer terminals for connecting capacitors. It also has several advantages.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional phase synchronization circuit, Fig. 2 is a block diagram showing an embodiment of the present invention, Figs. 3 and 4 are waveform diagrams of main parts, and Fig. 5 is another embodiment. FIG. 6 is a circuit diagram of the main parts. 1... Voltage controlled oscillator, 2... Phase comparator, 3... Video detector, 5... Low pass filter, 6... ... Phase shifter, 7 ... Level comparator, 8 ... First waveform shaping circuit, 9 ...
...Second waveform shaping circuit, 10...Integrator.

Claims (1)

[Claims] 1. A voltage-controlled oscillator whose oscillation frequency is controlled by a control voltage; a first phase-locked loop consisting of a phase comparator, and the phase comparator has a carrier frequency of approximately π/2 of the input signal.
(rad) a second phase comparator that operates on different phase axes, and a first level comparator whose operation start point is set by a first reference voltage that is DC-coupled to its output terminal. , a first waveform shaping circuit that converts the output of the comparator into the sawtooth wave signal, and a second waveform shaping circuit that converts the output of the shaping circuit into a substantially rectangular wave signal. and a second phase control loop in which the output of the second waveform shaping circuit is supplied to the voltage controlled oscillator via an integrator. 2. The phase locked circuit according to claim 1, wherein the voltage controlled oscillator is controlled by a substantially DC component of the output of the low-pass filter and an AC component of the output of the integrator. 3. The first waveform shaping circuit includes a charging circuit configured to input the output of the first level comparator and charge a capacitor at a predetermined time constant; The second waveform shaping circuit includes a reference voltage generation circuit configured to switch between two different DC outputs, and a reference voltage generation circuit configured to switch between the output and the first waveform shaping circuit. and a second level comparator for comparing the output values, and the output of the level comparator controls the reference voltage generation circuit and the discharge circuit, and the output is compared with the output of the second waveform shaping circuit. A phase-locked circuit according to claim 1. 4. Claim 1, wherein the integrator has a charge/discharge time constant set so as to convert an input substantially rectangular wave signal supplied from the second waveform shaping circuit into a substantially sawtooth wave signal. The phase-locked circuit described. 5. A patent in which the discharge circuit includes a first discharge circuit whose discharge operation is controlled by the output of the second level comparator, and a second discharge circuit having a constant discharge time constant. A phase locked circuit according to claim 3. 6. The phase locked circuit according to claim 4, wherein the integrator is constituted by a transistor and a parallel connection circuit of an integrating capacitor connected to the emitter of the transistor and a discharge resistor. 7 A voltage-controlled oscillator whose oscillation frequency is controlled by a control voltage, and a first phase comparator that supplies the control voltage to the oscillator via a low-pass filter using the amplitude-modulated signal as an input signal. In addition to having a phase-locked loop,
The phase comparator is approximately π at the carrier frequency of the input signal.
/2 (rad) A second phase comparator that operates on different phase axes, and a first level comparator whose operation start point is set by the first reference voltage when DC coupled to the output terminal of the second phase comparator. and a first waveform shaping circuit that converts the output of the comparator into a substantially sawtooth wave signal, and a second waveform shaping circuit that converts the output of the shaping circuit into a substantially square wave signal, the output of which is A phase synchronization circuit comprising a phase synchronization detection circuit that outputs an output via an integrator. 8. The phase locked circuit according to claim 7, wherein the integrator is constituted by a peak value rectifier circuit.