JPS6161297B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase synchronization device having a phase control loop, and in particular, to prevent the detection operation from being disturbed by external pulse noise when detecting the synchronization or non-synchronization state of the phase control loop. The purpose is to

A phase synchronization state detection method related to the present invention includes a phase synchronization device disclosed in Patent Application No. 154627/1983 by the present applicant. In this device, the first
a phase comparator, and a second phase comparator (i.e., an in-phase demodulator) that operates on a phase axis different from the first phase comparator by π/2 (rad), and It is described that the rectifier circuit for detecting the synchronization state on the output side of the phase comparator is selected so that its rectification polarity is opposite to the demodulation polarity of the second phase comparator described above. It is preferable that the above rectifier circuit be configured as a peak rectifier circuit in order to increase the detection sensitivity of the phase synchronization state and to speed up the detection response speed. However, when applying such a phase synchronization device to a radio receiver, is obtained at the output of the second phase comparator when an extraneous pulsed noise, such as ignition noise, causes a phase reversal of π (rad) in the radio frequency carrier, especially when the phase control loop is in lock. Among the noises contained in the amplitude demodulated signal, the noise generated in the zero carrier direction exceeds the zero carrier level, which sometimes makes the synchronization state detection operation unstable.

The present invention eliminates the above-mentioned drawbacks and makes the synchronization detection operation extremely stable, and will be described below with reference to the drawings showing embodiments.

FIG. 1 shows the basic configuration of this invention. This device includes a phase control loop consisting of a first phase comparator 1, a low-pass filter 2, and a voltage-controlled oscillator 3, and further includes a π/2 (rad) phase shifter 4, a The amplitude synchronization demodulator 10 includes two phase comparators 5, and a tuning detector 20 includes a rectifier circuit 6, a noise detector 7, and a discharge circuit 8.

When the phase control loop is in an asynchronous state at the output terminal _T2 of the amplitude synchronous demodulator 10, the average linear level, that is, the zero carrier level is _V0 as shown in FIG. Carrier wave ₁ of input signal ₁ and output signal of voltage controlled oscillator 3
An amplitude-modulated signal waveform (beat signal) converted to _a difference of _1-2 from ₂ is obtained. Next, when the phase control loop enters the synchronized state, either the envelope a' or a'' in Figure 3a mentioned above is obtained as the demodulated output at the output terminal _T2 .
Suppose we get the a′ side. FIG. 3b shows the signal waveform containing noise at this time.

Here, the rectifier circuit 6 in FIG. 1 uses the zero carrier level V ₀ shown in FIG. 3 as a reference and when a level higher than V ₀ occurs at the output terminal T ₂ of the second phase comparator 5. Start charging the capacitor.

For example, when a beat signal as shown in FIG. 3a is applied (asynchronous state), when rectifying the a'' side, a DC level of approximately V ₁ is obtained at the output end of the rectifier circuit 6 by peak rectification. This operation is the same even when the phase control loop is in a synchronized state, that is, when amplitude synchronized demodulation is performed normally, and as shown in Figure 3b, the level of the zero carrier wave is affected by RF pulse noise. If noise V _N1 exceeding V ₀ occurs in the demodulated output, approximately V ₁ will appear at the output terminal of the rectifier circuit 6.
The operation starts to generate a DC level of .

On the other hand, since noise normally occurs in the form of noises V _N1 and V _N2 in both directions, the noise detection circuit 7 uses the level of V ₂ shown _in FIG _. It detects the presence of noise and generates a pulse. The noise pulse detected by the noise detection circuit 7 starts the operation of the discharge circuit shown at 8 in _FIG . Discharge the components. The charging operation of the rectifier circuit 6 due to the above-mentioned pulsed noise V _N1 has a relatively narrow pulse width, so it is not possible to completely charge the rectifier circuit 6 with only a single pulse, and the DC level is gradually increased by repeated charging, and the final Specifically, a DC level of approximately V ₁ is generated at the output end.

Note that even in the asynchronous case where a beat signal as shown in _{FIG .} The discharge circuit 8 starts its operation by the output pulse of the detection circuit 7, but since the charging period with the beat signal is longer than the period of instantaneous discharging due to pulse noise, its influence is ignored. can.

A specific example of the configuration of the synchronization detector 20 of the above embodiment is shown in FIG. Transistor Q ₁ with capacitor C ₁ connected to its emitter constitutes a peak rectifier circuit, and in order to make the charging time constant much smaller than the discharging time constant, an emitter follower circuit consisting of transistor Q ₂ and resistor R ₃ is placed at the output. are doing. The dividing circuit with resistors R ₁ and R ₂ is a transistor
In order to determine the starting point of _Q1 's operation, a predetermined DC bias is applied to its emitter. Connect the collector to the emitter of transistor _Q1 ,
The transistor _Q3 whose emitter is grounded constitutes a switch circuit for discharging, and its operation is controlled by the output of the noise detection circuit 7. The circuit operation in FIG. 2 is the same as that explained in FIG. 1, so a detailed explanation will be omitted, but the circuit configuration can be modified in various ways. For example, the transistor for peak rectification or the switching transistor for discharge may be replaced by another, e.g. PNP
It can be easily realized using a type or field effect transistor, and is not limited to the specific configuration shown in FIG.

According to the above embodiment, when the rectifier circuit 6 for synchronization detection is configured with a peak rectifier circuit, the electric charge charged in the rectifier capacitor by the pulse noise in the direction exceeding the zero carrier level of the demodulated output is transferred in the reverse direction. This type of synchronization detection circuit detects the noise and discharges it through the discharge circuit 8, making the operation of this type of synchronization detection circuit extremely stable. Furthermore, since it can be realized entirely with an amplitude detection configuration, a direct circuit configuration is easy, and it is suitable for integrated circuit implementation. In addition, when the output of the synchronization detector 20 is guided to a circuit that drives the amplitude synchronization demodulator 10 in the direction of synchronization when it is out of synchronization, or when it is applied to a display device, etc., malfunctions due to the pulse noise can be eliminated, etc. It has also become possible to greatly improve the reliability of connections with circuits.

As described above, the present invention provides an excellent phase synchronization device whose synchronization detection operation is extremely stable against external pulse noise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the phase synchronization device of the present invention, FIG. 2 is a circuit diagram of the main part, and FIG. 3 is a waveform diagram of the main part. DESCRIPTION OF SYMBOLS 1... Phase comparator, 2... Low pass filter, 3... Voltage controlled oscillator, 4... Phase shifter, 5... Phase comparator, 6...
Rectifier circuit, 7... Noise detection circuit, 8... Discharge circuit.

Claims (1)

[Claims] 1. A voltage controlled oscillator whose oscillation frequency is controlled by a control voltage, and a first phase comparison using an output signal of the voltage controlled oscillator and an amplitude modulated input signal as inputs. a low-pass filter that smooths the output of the first phase comparator and inputs it to the voltage-controlled oscillator, and a phase shifter that shifts the input signal and the output signal of the voltage-controlled oscillator by π/2 (rad). a second phase comparator which receives the signal as input, and a synchronization detection circuit that detects the phase synchronization state of the voltage-controlled oscillator by a rectification action having a polarity opposite to the demodulation polarity in the second phase comparator. a noise detection circuit that configures the synchronization detection circuit with a peak rectification circuit and detects noise in the signal applied to the synchronization detection circuit in a direction that causes the rectification operation to stop; A phase synchronization device comprising: a discharge circuit that is driven by an output signal of the noise detection circuit and discharges the charge in the filtering capacitor of the peak rectification circuit.