JPS6247005B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplitude locked detection circuit configured using a phase locked loop, and particularly aims to provide a circuit that can accurately detect the phase locked state of the loop. .

A phase-locked state detection circuit (hereinafter abbreviated as a synchronization detection circuit) is arranged for the purpose of detecting the state of a phase-locked loop for synchronizing the oscillation frequency and phase of a voltage-controlled oscillator with an incoming input signal. , its output can be used, for example, as a driving signal for a muting or indicator circuit,
Alternatively, it can be used in various ways, such as as a switching signal for a loop filter in a phase-locked loop.

Applications to wireless equipment include various factors that impede practical application, such as changes in the level of incoming input signals and interference due to radio frequency pulse noise, and highly stable synchronization detection circuits are required to counter these factors. It has become necessary. An example of such a synchronization detection circuit is shown in FIG. 1 and described in Japanese Patent Laid-Open No. 53-78153, which will be described below with reference to the drawings.

In FIG. 1, a phase-locked loop consisting of a voltage-controlled oscillator 1, a first phase comparator 2, and a low-pass filter 3, a second phase comparator 41, and a level comparator 42 is shown.
and a low-pass filter 43.
It is shown that it is constructed by In this circuit, the second phase comparator 41 substantially acts as either an amplitude locked detector or a frequency converter depending on whether the phase locked loop is synchronous or unsynchronized. Differences in signal waveforms are detected by an amplitude separation type level comparator 42, and the average value or approximately the peak value of the output is used as a detected output signal.

A synchronization detection circuit having such a configuration is likely to malfunction because it responds to pulse noise mixed in the incoming input signal, and when the input signal reaches a weak level, the output of the detector is caused by the synchronization of the phase-locked loop. For example, the indicator circuit is driven in the same mode as when the loop is synchronous even when there is no signal.

The present invention has been made in view of the above-mentioned practical drawbacks, and specifically aims to provide a synchronization detection circuit that does not malfunction due to pulse noise mixed in an incoming input signal. be.

The synchronization detection circuit based on the present invention has first and second phase comparators similar to the conventional circuit example, each of which constitutes a phase comparator and an amplitude synchronized detector in a known phase-locked loop. π/
A difference in operating phase of 2 (vad) is given. The synchronization detection circuit is composed of a low-pass filter and a level comparator arranged on the output side of the second phase comparator, that is, the amplitude synchronized detector, and the reference level of this comparator is set at the output side of the amplitude synchronized detector. The output signal of the phase-locked loop is set within the range of approximately average DC levels corresponding to the synchronous and asynchronous states of the phase-locked loop, and is further set at the input signal end of the low-pass filter, that is, the output signal end of the amplitude-locked detector. This has the feature that the approximately linear operating ranges for all amplitude information in the positive and negative directions (including signal and noise components) are set approximately equal, with the DC level corresponding to the zero carrier level as the reference. There is.

Hereinafter, details of the present invention will be explained with reference to the drawings.

FIG. 2 shows the basic configuration of a synchronization detection circuit based on the present invention. Components having the same functions as those in FIG. 1 are designated by the same reference numerals.

The amplitude synchronous detector 44 is basically the same as the conventional one, but the operating range at its output terminal is set so that the positive and negative directions are approximately equal with respect to the zero carrier level _E0 as shown in FIG. to each
Limited to E ₁ and E ₂ . To limit this operating range, for example _, as shown in _FIG .
An amplitude limiter consisting of 1,442 is arranged. A transistor 44 constitutes an amplitude synchronous detector using pulse noise components mixed into the incoming input signal _S1 .
When 3,444 is saturated, the amplitude of the output noise component becomes asymmetric in the positive direction and the negative direction with respect to the DC operating point, but the above-mentioned amplitude limiter converts this into a symmetrical one. do.

For example, when the phase-locked loop is synchronized, the output terminal _T1 in FIG. 4 receives a detected signal V _S as shown in FIG. 3 A and a noise component V _N superimposed on this signal.
(only one cycle is shown in the figure) occurs. If the superimposed noise V _N is not limited in amplitude by a phase comparator or any other signal processing circuit, its average DC level will be equal to the instantaneous DC level of the signal V _S . However, all conventional circuits including the phase comparator and the signal processing circuits before and after the phase comparator have a relatively narrow operating range, making the amplitude of the arriving noise component asymmetrical. As a result, the average DC level of the composite amplitude information of the beat signal V _S ' in FIG. 3B and the noise component V _N ' superimposed thereon, which occurs when the phase-locked loop is in an asynchronous state, shifts instantaneously. In the present invention, since this average DC level is constant, the output terminal of the low-pass filter 45 has the advantage that the DC level corresponding to the asynchronous state of the phase-locked loop can be maintained at E ₀ even instantaneously. Therefore, since the reference level of the level comparator 46 can be set between E ₀ and E ₂ in FIG. 3 and very close to E ₀ , even minute levels of the incoming input signal can be reliably detected. Not only this, but also stable detection is possible even with high modulation, for example, for negative modulation television signals.

FIG. 5 shows another configuration example of the present invention. This figure shows that an amplifier 47 is arranged to amplify the detection output signal to a predetermined level, and that the signal is supplied to a low-pass filter 45 via an amplitude limiter 48. The amplifier 47 may include transistors 471, 472, 47, as shown in FIG.
3 and 474, a diode 475, and load resistors 476 and 477,
An excessive noise component in the negative direction caused by the asymmetry of the linear operating regions in the positive and negative directions with the zero carrier wave DC level as a reference of approximately V _CC /Z is generated by the transistor 478 to which a DC bias E _B is applied to the base electrode. As explained above with reference to FIG. 3, the noise is clipped to become substantially symmetrical noise.

As described above, the present invention provides a substantially linear operation in the positive and negative directions with respect to the zero carrier level when supplying the output signal of the amplitude synchronous detector to the low-pass filter configured to obtain its substantially average value. This device has an amplitude limiting means so that the regions are approximately symmetrical, thereby obtaining a signal that does not respond to pulse noise at the output of the low-pass filter, and outputting a phase signal to the output end of the level comparator. It is configured to obtain a detection output signal corresponding to the same or asynchronous state of the synchronous loop. Therefore, even if the incoming input signal is weak and contains pulse noise, it is not only possible to accurately detect the synchronous state, but also to generate a detection output in the same mode as an asynchronous state when the input signal level falls below a practical level. It has great industrial value, as it is suitable for use as a driving signal for muting or reception indicators.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional example of a synchronous state detection circuit, FIGS. 2 and 5 are block diagrams of a synchronous state detection circuit according to an embodiment of the present invention, FIG. 3 is a waveform diagram used for explanation, and FIG. The figure and FIG. 6 are specific circuit diagrams thereof. 1... Voltage controlled oscillator, 2... First phase comparator, 3... Low pass filter, 44... Amplitude synchronous detector, 45... Low pass filter, 46... Level comparator .

Claims (1)

[Claims] 1. An amplitude synchronized detection means configured using a phase-locked loop, an amplitude limiting means disposed on the output side of the detection means, and a low-pass filtering means coupled to the output terminal thereof. , at least level comparison means to which the output signal of the filtering means is supplied and selected to have substantially the same detection polarity as the detection means, and the low-pass filtering means has a substantially average value of the input signal. A phase synchronization state detection circuit characterized in that it is configured to obtain the following. 2. The amplitude synchronous detection means includes an amplifier having at least one stage arranged on the output side thereof, and at least one amplitude limiter arranged on the output side of the amplifier reduces the pulse noise mixed in the incoming input signal to the zero carrier level. 2. The phase synchronization state detection circuit according to claim 1, wherein the phase synchronization state detection circuit is configured to be substantially symmetrical with respect to .