JPS625782A - Synchronous separator - Google Patents

Abstract

PURPOSE:To assure a separation of synchronous signals even when sag of vertical scanning cycle incidentally occur in an image detecting output by providing a slice level variable means which make slice levels of a synchronizing and separator circuit variable. CONSTITUTION:The slice level variable means is composed of a differential amp circuit 13 of a synchronous separator 11, peak detecting circuits 14 and 17, a reverse amplifier circuit 16, an integration circuit 15, a single monostable multivibrator 18 and the like. When a vertical synchronous signal a composite in video signal which is an output of an image detecting circuit 4 occur the sag and direct current level becomes larger during vertical synchronous period, an emitter potential of transistor Q1 of synchronous separator circuits 12 rises and allows the transistor Q2 to repeat ON and OFF and then outputs of the peak detecting circuits 14 to develop ripples. The ripple current is detected and rectified by the peak detecting circuit 17 and allow the transistor Q6 to rise a base potential. Then the transistor Q6 becomes to be ON during a vertical blanking period and permit a base bias of the transistor Q1 to be lowered and also the synchronous signal to be separated from the video signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sync separator that can stably separate a sync signal against a sag in a vertical scanning period.

[Conventional technology]

The television reception ff1l shown in FIG. 3 receives the television signal tuned by the tuning circuit 2.

The video signal is supplied to the video detection circuit 4 via the video intermediate frequency amplification circuit 3, and the detected video signal is supplied to the picture tube 6 via the video signal processing circuit 5, while the synchronization separation circuit 7 connected to the video detection circuit 4 The configuration is such that separated horizontal and vertical synchronization signals are supplied to the horizontal output circuit 8a and the vertical output circuit 9a via the horizontal oscillation circuit 8 and the vertical rooting circuit 9, respectively, and is generally a well-defined circuit configuration.

[Problem that the invention seeks to solve]

In the conventional television receiver 1 described above, if a sag in the vertical scanning period is parasitic for some reason in the video detection output that is the output of the video detection circuit 4, the vertical synchronization signal will not be separated in the synchronization separation circuit 7. , the image displayed on the picture tube 6 flows vertically.

There were problems such as causing so-called synchronous flow.

[Means for solving problems]

This invention solves the above problems.

A sync separation circuit with a variable slice level for separating the amplitude of a sync signal from a composite video signal in which a sync signal is combined with a video signal, a peak detection circuit that detects the output peak of this sync separation circuit, and a vertical block. The present invention comprises a slice level variable means that operates depending on the presence or absence of an output of the peak detection circuit within a ranking period and varies the slice level of the synchronization separation circuit so that vertical synchronization signals can be separated. It is something.

[Effect]

This invention detects the output level of a synchronization separation circuit that amplitude-separates a synchronization signal in a combined video signal using a peak detection circuit, and depending on the presence or absence of the output of the peak detection circuit within a vertical blanking period, To always and reliably separate vertical synchronization signals by varying the slice level of a synchronization separation circuit.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1.2 is a circuit diagram and a signal waveform diagram of each part of the circuit, respectively, showing an embodiment of the synchronous separator of the present invention.

In FIG. 1, the sync separator 11 is configured to automatically correct the slice level of the sync signal separated by the sync separator 12 at a vertical scanning period. The synchronization separation circuit 12 separates the amplitude of the synchronization signal in the composite video signal output from the video detection circuit 4 by using a pair of transistors Q, Q, whose emitters are connected via a resistor R1.
A composite video signal is input to the base of one transistor Q1, and one voltage dividing resistor R,, R,
A constant base voltage is applied. Note that the base bias of the transistor Q is determined by a resistor and a differential amplifier circuit 13, which will be described later.

For the resistance between the transistor Q and the emitter of the parrot, a series connection circuit of a resistor 5 and a capacitor CI is connected in parallel. A horizontal oscillation circuit 8 is connected to the collector of the transistor Q.
A peak detection circuit 14 and an integration circuit 15 are connected through a transistor Q3 which supplies an emitter output to the vertical oscillation circuit 9, and an inversion circuit 12a.

The peak detection circuit 14 has a configuration in which a capacitor C1 for peak hold is connected in parallel to the emitter resistor R0 of a transistor Q4 whose base input is the collector output of the transistor Q. 7 through another peak detection circuit. This other peak detection circuit 17 has a peak hold capacitor C connected to the emitter resistor R of a transistor Q whose base input is the output of the one-inverting amplifier circuit 16.
3 are connected in parallel, and its emitter output becomes the base input of one transistor Q6 in the differential amplifier circuit 13.

The integrating circuit 15 is for frequency-separating the vertical synchronizing signal from the horizontal synchronizing signal, and its output is as follows.

The differential amplifier circuit 1
It is input to the base of the other transistor Q in 3.

The differential amplifier circuit 13 includes the pair of transistors Qs
, Q, are commonly connected and grounded via a constant current transistor Q8.The collector of transistor Q6 is connected to the base of transistor Q1, while the collectors of nine transistors are connected to the power supply line. Connected.

Note that in this embodiment, the differential amplifier circuit 13. Peak detection circuit 14, 1? , inverting amplifier circuit 16. Integrating circuit 15. The monostable multivibrator 18 and the like constitute slice level variable means.

Now, when a composite video signal with no fluctuation in the signal level of the vertical synchronization signal is being sent from the video detection circuit 4, the transistor Q1 in the synchronization separation circuit 12 is conductive during periods other than the synchronization signal period, so the transistor Q snow conducts only during the synchronization signal period. As a result, the output of the peak detection circuit 14 becomes a pulse having a peak during the synchronization signal period, and its polarity is inverted via the 1-inversion amplifier circuit [6]. The output of this inverting amplifier circuit 16 is input to a peak detection circuit 17, and is output as a signal having a similar waveform although the polarity is different from that of the output of the peak detection circuit 14.

By the way, when the output of the peak detection circuit 17 is input to the base of one transistor Q in the differential amplifier circuit 13, the base of the other transistor Q is connected to a monostable transistor triggered by a vertical synchronizing signal. Multi vibrator 1
The output of 8 is input. Therefore, one transistor Q,
, Q, there is virtually no change in the differential input, and the collector current ratio also does not change.Therefore, the base bias of the transistor Q1 in the synchronous separation circuit 12 does not change either.
The synchronous separation operation continues as before.

On the other hand, assume that the vertical synchronization signal in the composite video signal causes a sag, and the DC level of the signal increases during the vertical synchronization period, as shown in FIG. 2(A). In this case, as the sag occurs, the emitter potential of the transistor Q1 in the synchronization separation circuit 12 increases during the vertical synchronization period. As a result, the transistor Q, which had been always conductive during the synchronization signal period, repeats conduction and non-conduction, and as shown in FIG. , is inverted and amplified into the signal waveform shown in FIG. 2(C), and rectified as the detection output of the peak detection circuit 17, raising the base magnetic potential of the transistor Q6.

Therefore, one transistor Q6 in the differential amplifier circuit 13 operates during the direct blanking period.

This causes the base bias of the transistor Qi in the sync separation circuit 12 to decrease during the vertical blanking period. Therefore, the synchronizing signal whose amplitude cannot be separated due to the occurrence of sag can be separated from the video signal as the base bias of the transistor Q1 decreases.

In this way, the synchronization separator 11 detects the output level of the synchronization separation circuit 12, which amplitude-separates the synchronization signal in the composite video signal, using the peak detection circuits 14 and 17, and detects the output level of the synchronization separator circuit 12, which separates the amplitude of the synchronization signal in the composite video signal, and detects the output level of the synchronization separator circuit 12, which separates the amplitude of the synchronization signal in the composite video signal. Since the slice level of the synchronization separation circuit 12 is varied depending on the presence or absence of the outputs of 14 and 17, and the vertical synchronization signal is separated, even if a sag in the vertical scanning period is parasitic in the video detection output, In the sync separation circuit 12 with a variable slice level, it is possible to reliably separate sync signals, and it is possible to prevent the inconvenience of sync flow on the picture tube screen due to poor sync separation.

〔Effect of the invention〕

As described above, according to the present invention, the output level of the synchronization separation circuit that separates the amplitude of the synchronization signal in the composite video signal is detected by the peak detection circuit.

Since the slice level of the synchronization separation circuit is varied depending on the presence or absence of the output of the peak detection circuit within the vertical blanking period, the vertical synchronization signal is separated.
Even if there is a sag in the vertical scanning period in the video detection output, the synchronization separation circuit with a variable slice level can reliably separate the synchronization signal, and the picture tube screen will be synchronized based on the defect in synchronization separation. This has excellent effects such as being able to prevent problems caused by flow.

[Brief explanation of drawings]

Figures 1.2 are a circuit diagram and signal waveform diagrams of various parts of the circuit, respectively, showing one embodiment of the synchronous separator of the present invention, and Figure 3 is:
1 is a circuit configuration diagram showing an example of a television receiver to which a conventional synchronization separation circuit is applied. 11... Synchronous separator, 12... Synchronous separator circuit, 13
...Differential amplifier circuit, 14, 17...Peak detection circuit, 15...Integrator circuit, 16...Amplifier circuit, 1
8... Monostable multivibrator.

Claims (1)

[Claims] A sync separation circuit with a variable slice level for separating the amplitude of the sync signal from a composite video signal in which a sync signal is combined with a video signal, a peak detection circuit that detects the output peak of this sync separation circuit, and a vertical A sync separator comprising slice level variable means that operates depending on the presence or absence of an output of the peak detection circuit within a blanking period and varies the slice level of the sync separator circuit so that vertical sync signals can be separated.