JPH036378U

JPH036378U -

Info

Publication number: JPH036378U
Application number: JP1989066618U
Authority: JP
Priority date: 1989-06-07
Filing date: 1989-06-07
Publication date: 1991-01-22

Description

[Brief explanation of the drawing]

第１図は、この考案の多画面デイスプレイ装置
の一実施例を示す概略回路構成図、第２図は、子
画面用映像信号と振幅分離レベルの関係を示す信
号波形図、第３，４図は、それぞれこの考案の多
画面デイスプレイ装置の他の実施例を示す概略回
路構成図、第５，６図は、それぞれ従来の多画面
デイスプレイ装置の一例を示す概略回路構成図及
び回路各部の信号波形図である。３……切り替え回路、１１……バツフアメモリ
、１２……画像メモリ、２１，３１，４１……多
画面デイスプレイ装置、２２……同期分離回路、
２３……分離レベル切り替え回路、３２……コン
トラスト調整回路、４３……白ピーク抑圧回路。 FIG. 1 is a schematic circuit configuration diagram showing an embodiment of the multi-screen display device of this invention, FIG. 2 is a signal waveform diagram showing the relationship between the sub-screen video signal and the amplitude separation level, and FIGS. 3 and 4 5 and 6 are schematic circuit diagrams showing other embodiments of the multi-screen display device of this invention, respectively, and FIGS. 5 and 6 are schematic circuit diagrams and signal waveforms of various parts of the circuit, respectively, showing an example of the conventional multi-screen display device. It is a diagram. 3...Switching circuit, 11...Buffer memory, 12...Image memory, 21, 31, 41...Multi-screen display device, 22...Synchronization separation circuit,
23...Separation level switching circuit, 32...Contrast adjustment circuit, 43...White peak suppression circuit.

Claims

[Claims for Utility Model Registration] (1) While intermittently synchronizing the video signal for the sub-screen with its synchronization signal, some lines are thinned out, written to the buffer memory, transferred to the image memory, and then included in the video signal for the main screen. A synchronization separation circuit that reads out a synchronization signal from a screen memory and inserts and displays it as a child screen in a part of a main screen while synchronizing with a synchronization signal, wherein the synchronization signal is separated from the video signal for the child screen by amplitude separation. and a separation level switching circuit that detects that the output of the sync separation circuit is no signal and rounds up the amplitude separation level of the sync separation circuit from the sync tip side to the video side up to the pedestal level. Multi-screen display device. (2) While intermittently synchronizing the video signal for the sub-screen with its synchronization signal, thin out several lines and write them to the buffer memory, transfer them to the image memory, and then write the video signal while synchronizing with the synchronization signal included in the main-screen video signal. A multi-screen display device which reads out an image from a memory and inserts and displays it as a child screen in a part of a main screen, and acts on a video signal for the child screen which is read out from the image memory and is inserted and displayed in a part of the main screen. , a multi-screen display device comprising a contrast adjustment circuit for adjusting the contrast of a sub-screen. (3) While intermittently synchronizing the video signal for the sub-screen with its synchronization signal, thin out several lines and write them to the buffer memory, transfer them to the image memory, and then synchronize with the synchronization signal included in the main-screen video signal, A multi-screen display device that reads data from a memory and inserts and displays it as a sub-screen in a part of a main screen, the multi-screen display comprising a white peak suppression circuit that acts on a sub-screen video signal to suppress white peaks. Device.