JPS63163067U - - Google Patents

Description

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a composite synchronizing signal generation circuit for video equipment according to an embodiment of this invention, Fig. 2 is a circuit diagram showing the same circuit in detail, and Fig. 3 shows half-row dot pattern data in this embodiment. 4, 5, and 6 a to d are timing charts for explaining the operation of the circuit of this embodiment, and FIGS. 7 to 13 are timing charts showing conventional composite synchronization for video equipment. Fig. 7 is a block diagram of the signal generation circuit, Fig. 8 is a schematic diagram for explaining a general image configuration using scanning lines, Fig. 9 a, b, Figs. 10 to 12, and Fig. 13
Figures a to d are timing charts for explaining the operation of the conventional circuit. In the figure, 2...Synchronization signal generation circuit, 10...Composite synchronization signal generation circuit for video equipment, 11...Timing synchronization circuit, 12...Half line counter, 13...Half line pattern memory, 15...Half line dot counter, 16
...Half-row dot pattern memory, 20...Output circuit.
In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of utility model registration request] A composite synchronization signal generation circuit for video equipment that generates a composite synchronization signal to the video equipment, a synchronization signal generation circuit that generates a video signal clock, a horizontal synchronization signal, a 1/2 synchronization signal of the horizontal synchronization signal, and a vertical synchronization signal; A timing synchronization circuit receives a signal from the synchronization signal generation circuit and outputs a counter reset timing signal, and counts 1/2 synchronization signal of the horizontal synchronization signal and uses the counter reset timing signal from the timing synchronization circuit. A half-row counter that is reset at a required timing, and a half-row pattern memory that stores required half-row pattern data and outputs half-row pattern data in accordance with the output from the half-row counter are provided. a half-row dot counter that counts the video signal clock for a row and is reset at a required timing by a counter reset timing signal from the timing synchronization circuit;
A half-row dot pattern memory is provided which stores required half-row dot pattern data and outputs half-row dot pattern data according to the output from the half-row dot counter. 1. A composite synchronization signal generation circuit for video equipment, comprising an output circuit for synchronizing data from a pattern memory with the video signal clock and outputting the synchronization signal as a composite synchronization signal.