JPS6392474U - - Google Patents
Info
- Publication number
- JPS6392474U JPS6392474U JP18659486U JP18659486U JPS6392474U JP S6392474 U JPS6392474 U JP S6392474U JP 18659486 U JP18659486 U JP 18659486U JP 18659486 U JP18659486 U JP 18659486U JP S6392474 U JPS6392474 U JP S6392474U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- horizontal
- vertical synchronization
- image signal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
Landscapes
- Studio Circuits (AREA)
Description
第１図は本考案の要部を示す同期信号補正回路
のブロツク図、第２図は第１図の具体的回路図、
第３図は第１図及び第２図の回路が適用された本
になるスーパーインポーズ装置のブロツク図、第
４図は第２図の回路図を説明する為のタイミング
チヤートを夫々示す。
１……水平同期信号の２周期検出回路、２……
水平同期信号の６周期検出回路、３……ＯＲゲー
ト、４……分周回路、１０……ＶＴＲの同期分離
回路、１９……パソコンの同期分離回路、１１…
…垂直同期補正回路。
Fig. 1 is a block diagram of a synchronizing signal correction circuit showing the main part of the present invention, Fig. 2 is a specific circuit diagram of Fig. 1,
FIG. 3 is a block diagram of a superimposing device to which the circuits of FIGS. 1 and 2 are applied, and FIG. 4 is a timing chart for explaining the circuit diagram of FIG. 2. 1... 2-cycle detection circuit for horizontal synchronization signal, 2...
6-cycle detection circuit for horizontal sync signal, 3...OR gate, 4...frequency divider circuit, 10...sync separation circuit for VTR, 19...sync separation circuit for personal computer, 11...
...Vertical synchronization correction circuit.
Claims (1)
信号とを合成するスーパーインポーズ装置におい
て、 パソコンの水平及び垂直同期信号から水平同期
信号の２周期の時間を検出する手段と、 該パソコンの水平及び垂直同期信号とＶＴＲの
垂直同期信号から水平同期信号の６周期の時間を
検出する手段と、 該２周期及び６周期の各時間を加算する回路と
、 該加算回路から出力される時間だけ該画像信号
発生装置のドツトクロツクの周波数を１／２に分
周する回路とで構成した事を特徴とするスーパー
インポーズ装置。[Claims for Utility Model Registration] In a superimposing device that synthesizes a video signal reproduced by a VTR and an image signal from an image signal generator, means for detecting the time of two periods of a horizontal synchronization signal from horizontal and vertical synchronization signals of a personal computer. and means for detecting the time of six periods of the horizontal synchronization signal from the horizontal and vertical synchronization signals of the personal computer and the vertical synchronization signal of the VTR, a circuit for adding the times of each of the two and six cycles, and from the adding circuit. 1. A superimposing device comprising a circuit that divides the frequency of a dot clock of the image signal generating device into 1/2 for the output time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18659486U JPS6392474U (en) | 1986-12-03 | 1986-12-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18659486U JPS6392474U (en) | 1986-12-03 | 1986-12-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6392474U true JPS6392474U (en) | 1988-06-15 |
Family
ID=31136292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18659486U Pending JPS6392474U (en) | 1986-12-03 | 1986-12-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6392474U (en) |
-
1986
- 1986-12-03 JP JP18659486U patent/JPS6392474U/ja active Pending
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