JPS6454467U - - Google Patents
Info
- Publication number
- JPS6454467U JPS6454467U JP14840487U JP14840487U JPS6454467U JP S6454467 U JPS6454467 U JP S6454467U JP 14840487 U JP14840487 U JP 14840487U JP 14840487 U JP14840487 U JP 14840487U JP S6454467 U JPS6454467 U JP S6454467U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- circuit
- signal
- synchronization
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims 4
- 230000001960 triggered effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
Landscapes
- Picture Signal Circuits (AREA)
Description
第１図はこの考案に係るＣＲＴ表示装置のクラ
ンプパルス発生回路の一実施例を示す回路図、第
２図は従来のクランプパルス発生回路の一例を示
す回路図、第３図はクランプパルスと映像信号の
タイミングを示すタイムチヤートである。
１１……映像入力端子、１２……同期信号入力
端子、１３……同期分離回路、１４，１５……単
安定マルチバイブレータ回路、１６……積分回路
、１７……オアゲート、Ｄ……ダイオード。
Fig. 1 is a circuit diagram showing an example of a clamp pulse generation circuit for a CRT display device according to this invention, Fig. 2 is a circuit diagram showing an example of a conventional clamp pulse generation circuit, and Fig. 3 shows clamp pulses and images. This is a time chart showing the timing of signals. 11... Video input terminal, 12... Synchronous signal input terminal, 13... Synchronous separation circuit, 14, 15... Monostable multivibrator circuit, 16... Integrating circuit, 17... OR gate, D... Diode.
Claims (1)
を別系統の線路によつて伴つているセパレート映
像信号とが選択的に入力されるＣＲＴ表示装置に
おいて、 前記複合映像信号及びセパレート映像信号が導
かれる第１の端子と、 前記セパレート映像信号に伴つた同期信号が導
かれる第２の端子と、 前記第１の端子からの複合映像信号が入力され
この信号を同期分離して同期信号を出力する同期
分離回路と、 前記同期分離回路からの同期信号が入力されこ
の同期信号の水平周期のパルス成分でトリガされ
て所定幅のクランプ用パルスを発生する第１の回
路と、 前記第２の端子からの同期信号の水平同期パル
ス成分によつてトリガされ所定幅のクランプ用パ
ルスを発生する第２の回路と、 セパレート映像信号の入力時に前記第２の端子
からの同期信号を利用して第１の回路の動作を禁
止する第２回路とを具備し、 これら第１及び第２の回路からの各クランプパ
ルスを複合映像信号入力時及びセパレート映像信
号入力時の共通のクランプパルスとするようにし
たことを特徴とするＣＲＴ表示装置のクランプパ
ルス発生回路。[Claims for Utility Model Registration] In a CRT display device to which a composite video signal containing a synchronizing signal and a separate video signal accompanying the synchronizing signal via a separate line are selectively input, said composite video signal and a first terminal to which a separate video signal is led, a second terminal to which a synchronization signal accompanying the separate video signal is led, and a composite video signal from the first terminal is input and the signals are synchronously separated. a synchronization separation circuit that outputs a synchronization signal from the synchronization separation circuit; a first circuit that receives the synchronization signal from the synchronization separation circuit and is triggered by a horizontal period pulse component of the synchronization signal to generate a clamping pulse of a predetermined width; a second circuit that generates a clamping pulse of a predetermined width triggered by a horizontal synchronizing pulse component of the synchronizing signal from the second terminal; and a second circuit that prohibits the operation of the first circuit by using the clamp pulses from the first and second circuits, and converts each clamp pulse from the first and second circuits into a common clamp pulse when inputting the composite video signal and when inputting the separate video signal. A clamp pulse generation circuit for a CRT display device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14840487U JPS6454467U (en) | 1987-09-30 | 1987-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14840487U JPS6454467U (en) | 1987-09-30 | 1987-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6454467U true JPS6454467U (en) | 1989-04-04 |
Family
ID=31419698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14840487U Pending JPS6454467U (en) | 1987-09-30 | 1987-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6454467U (en) |
-
1987
- 1987-09-30 JP JP14840487U patent/JPS6454467U/ja active Pending
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