JPS6398589U - - Google Patents
Info
- Publication number
- JPS6398589U JPS6398589U JP19464486U JP19464486U JPS6398589U JP S6398589 U JPS6398589 U JP S6398589U JP 19464486 U JP19464486 U JP 19464486U JP 19464486 U JP19464486 U JP 19464486U JP S6398589 U JPS6398589 U JP S6398589U
- Authority
- JP
- Japan
- Prior art keywords
- area
- image
- section
- video memory
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は、本考案をソナー装置に適用した場合
の一実施例の電気的構成を示すブロツク図、第２
図は第１図に示す第１のビデオメモリー部、第２
のビデオメモリー部およびクロツク制御部の詳細
な電気的構成を示すブロツク図、第３図は主要な
信号のタイミングを示すタイミングチヤート、第
４図は通常モードにおける表示画像を示す説明図
、第５図は拡大モードにおける表示画像を示す説
明図である。
１８……第１のビデオメモリー部、１９……第
２のビデオメモリー部、２０……クロツク制御部
、２６……ＣＲＴ表示部、５１……第１の画像、
５２……第２の画像、６１……第１のエリア、６
２……第２のエリア、２４２２……読み出しクロ
ツク。
FIG. 1 is a block diagram showing the electrical configuration of an embodiment of the present invention applied to a sonar device, and FIG.
The figure shows the first video memory section and the second video memory section shown in FIG.
3 is a timing chart showing the timing of the main signals, FIG. 4 is an explanatory diagram showing the display image in normal mode, and FIG. FIG. 2 is an explanatory diagram showing a display image in enlargement mode. 18...First video memory section, 19...Second video memory section, 20...Clock control section, 26...CRT display section, 51...First image,
52...Second image, 61...First area, 6
2...Second area, 2422...Read clock.
Claims (1)
割し、この分割されたエリアを第１のエリアおよ
ぶ第２のエリアとするとき、第１のエリアには第
１の画像、第２のエリアには第２の画像の表示を
行う表示装置であつて、 第１の画像のデーターの記憶と送出とを行う第
１のビデオメモリー部と、 第２の画像のデーターの記憶と送出とを行う第
２のビデオメモリー部と、 第１のエリアの広さと第２のエリアの広さとの
比率を設定する設定部と、 パルス毎に１画素の読み出しを行う読み出しク
ロツクであつて、前記設定部により設定された第
２のエリアの広さが狭くなるに従いそのパルスの
周期が短くなる読み出しクロツクを、第２のビデ
オメモリー部に送出するクロツク制御部とを備え
たことを特徴とする表示装置。[Claims for Utility Model Registration] When a CRT display section is divided into two in the horizontal scanning direction and the divided areas are defined as a first area and a second area, the first area has a first area and a second area. A display device that displays a first image and a second image in a second area, a first video memory unit that stores and transmits data of the first image, and a second area that displays a second image. a second video memory section that stores and sends data; a setting section that sets the ratio between the width of the first area and the width of the second area; and a readout clock that reads out one pixel for each pulse. and a clock control section that sends to the second video memory section a readout clock whose pulse cycle becomes shorter as the width of the second area set by the setting section becomes narrower. A display device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19464486U JPS6398589U (en) | 1986-12-17 | 1986-12-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19464486U JPS6398589U (en) | 1986-12-17 | 1986-12-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6398589U true JPS6398589U (en) | 1988-06-25 |
Family
ID=31151805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19464486U Pending JPS6398589U (en) | 1986-12-17 | 1986-12-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6398589U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61175680A (en) * | 1985-01-30 | 1986-08-07 | 富士通株式会社 | Display unit |
-
1986
- 1986-12-17 JP JP19464486U patent/JPS6398589U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61175680A (en) * | 1985-01-30 | 1986-08-07 | 富士通株式会社 | Display unit |
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