JPH02113170U - - Google Patents
Info
- Publication number
- JPH02113170U JPH02113170U JP2230089U JP2230089U JPH02113170U JP H02113170 U JPH02113170 U JP H02113170U JP 2230089 U JP2230089 U JP 2230089U JP 2230089 U JP2230089 U JP 2230089U JP H02113170 U JPH02113170 U JP H02113170U
- Authority
- JP
- Japan
- Prior art keywords
- address counter
- input
- points
- display
- display data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000009977 dual effect Effects 0.000 claims description 4
- 230000001360 synchronised effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
Description
第１図は本考案に係る波形表示装置の構成図、
第２図、第３図はその動作を説明する為のタイム
チヤート、第４図は補間回路の構成図、第５図は
その動作を説明する為のタイムチヤート、第６図
は補間回路の効果を説明する為の図、第７図は従
来の波形表示装置の構成図、第８図はデユアルポ
ートメモリの構成図である。
９…表示部、２０…デユアルポートメモリ、２
１…アドレスカウンタ、２２…フレームバツフア
制御回路、２３…補間回路。
FIG. 1 is a configuration diagram of a waveform display device according to the present invention,
Figures 2 and 3 are time charts to explain its operation, Figure 4 is a block diagram of the interpolation circuit, Figure 5 is a time chart to explain its operation, and Figure 6 is the effect of the interpolation circuit. FIG. 7 is a block diagram of a conventional waveform display device, and FIG. 8 is a block diagram of a dual port memory. 9...Display unit, 20...Dual port memory, 2
DESCRIPTION OF SYMBOLS 1... Address counter, 22... Frame buffer control circuit, 23... Interpolation circuit.
Claims (1)
モリと、このデユアルポートメモリにその行アド
レスを与えるアドレスカウンタと、表示部と、表
示データが入力され今回の表示データが表わす点
と前回の表示データが表わす点との間の点を補間
するデータを出力する補間部とを有し、前記アド
レスカウンタを前記表示部の水平同期信号に同期
した信号で駆動すると共に、この表示部の水平同
期期間中に前記補間回路の出力を前記入出力ポー
トを介して前記アドレスカウンタで指定された行
アドレスに格納するようにした事を特徴とする波
形表示装置。 A dual port memory that constitutes a frame buffer, an address counter that gives the row address to the dual port memory, a display section, and a point where display data is input and which points are represented by the current display data and the points represented by the previous display data. and an interpolation unit that outputs data for interpolating points between the two, and drives the address counter with a signal synchronized with the horizontal synchronization signal of the display unit, and the interpolation circuit drives the address counter with a signal synchronized with the horizontal synchronization signal of the display unit. 2. A waveform display device, characterized in that the output of the input/output port is stored at a row address specified by the address counter via the input/output port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2230089U JPH0717011Y2 (en) | 1989-02-28 | 1989-02-28 | Waveform display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2230089U JPH0717011Y2 (en) | 1989-02-28 | 1989-02-28 | Waveform display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02113170U true JPH02113170U (en) | 1990-09-11 |
| JPH0717011Y2 JPH0717011Y2 (en) | 1995-04-19 |
Family
ID=31240287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2230089U Expired - Lifetime JPH0717011Y2 (en) | 1989-02-28 | 1989-02-28 | Waveform display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0717011Y2 (en) |
-
1989
- 1989-02-28 JP JP2230089U patent/JPH0717011Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0717011Y2 (en) | 1995-04-19 |
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