JPS63135384U - - Google Patents
Info
- Publication number
- JPS63135384U JPS63135384U JP2652087U JP2652087U JPS63135384U JP S63135384 U JPS63135384 U JP S63135384U JP 2652087 U JP2652087 U JP 2652087U JP 2652087 U JP2652087 U JP 2652087U JP S63135384 U JPS63135384 U JP S63135384U
- Authority
- JP
- Japan
- Prior art keywords
- display
- circuit
- display data
- memory circuit
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
第１図は本考案の実施例における表示器を示す
ブロツク図、第２図は従来の表示装置のブロツク
図、第３図は従来の表示器を示すブロツク図であ
る。
１……制御回路、２，２′……表示器、３……
固有アドレス検出回路、４……表示記憶回路、５
……駆動回路、６……表示素子、７……共通アド
レス検出回路、８……固定表示データ回路、９…
…表示切替回路。
FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional display device, and FIG. 3 is a block diagram showing a conventional display device. 1...Control circuit, 2, 2'...Display device, 3...
Unique address detection circuit, 4...Display storage circuit, 5
...Drive circuit, 6...Display element, 7...Common address detection circuit, 8...Fixed display data circuit, 9...
...Display switching circuit.
Claims (1)
制御回路と、前記表示データ信号の取り込みを行
なう表示記憶回路、前記表示制御信号を取り込み
自己のアドレスが検出されたならば前記表示記憶
回路に前記表示データの取り込みを指令する固有
アドレス検出回路、取り込まれた表示データを表
示する表示手段、および前記制御回路から前記表
示制御信号によつて送出された共通のアドレスを
検出して前もつて困定的に設定された表示データ
を表示する表示手段とを有し、前記制御装置から
共通アドレスによる表示動作を指令することによ
つて、各前記表示器の動作を同時に確認できるよ
うにしたことを特徴とする表示装置。 a control circuit that outputs a display data signal and a display control signal; a display memory circuit that captures the display data signal; and a display memory circuit that captures the display control signal and stores the display data in the display memory circuit when its own address is detected. A unique address detection circuit for instructing capture, a display means for displaying the captured display data, and a common address sent from the control circuit by the display control signal is detected and set in advance. display means for displaying the displayed display data, and the display is characterized in that the operation of each of the display devices can be confirmed simultaneously by commanding the display operation using a common address from the control device. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2652087U JPS63135384U (en) | 1987-02-24 | 1987-02-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2652087U JPS63135384U (en) | 1987-02-24 | 1987-02-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63135384U true JPS63135384U (en) | 1988-09-06 |
Family
ID=30827676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2652087U Pending JPS63135384U (en) | 1987-02-24 | 1987-02-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63135384U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02245895A (en) * | 1989-03-17 | 1990-10-01 | T I Shii Shichizun:Kk | Two-wire display device |
-
1987
- 1987-02-24 JP JP2652087U patent/JPS63135384U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02245895A (en) * | 1989-03-17 | 1990-10-01 | T I Shii Shichizun:Kk | Two-wire display device |
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