JPS62191267U - - Google Patents

Info

Publication number
JPS62191267U
JPS62191267U JP7698886U JP7698886U JPS62191267U JP S62191267 U JPS62191267 U JP S62191267U JP 7698886 U JP7698886 U JP 7698886U JP 7698886 U JP7698886 U JP 7698886U JP S62191267 U JPS62191267 U JP S62191267U
Authority
JP
Japan
Prior art keywords
clock pulse
amplitude
adjustment circuit
level adjustment
output level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7698886U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7698886U priority Critical patent/JPS62191267U/ja
Publication of JPS62191267U publication Critical patent/JPS62191267U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案によるMOS形イメージセンサ
の出力信号レベル調整回路の一実施例、第2図は
MOS形イメージセンサ駆動用クロツクパルスの
タイミングチヤート、第3図は従来のMOS形イ
メージセンサの基本回路構成を示す図である。 1…フオトダイオード、2…MOSスイツチン
グトランジスタ、3…垂直シフトレジスタ、4…
水平シフトレジスタ、5…センサ駆動回路。
Fig. 1 shows an example of an output signal level adjustment circuit for a MOS image sensor according to the present invention, Fig. 2 shows a timing chart of a clock pulse for driving a MOS image sensor, and Fig. 3 shows a basic circuit of a conventional MOS image sensor. FIG. 3 is a diagram showing the configuration. 1...Photodiode, 2...MOS switching transistor, 3...Vertical shift register, 4...
Horizontal shift register, 5...sensor drive circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 1水平走査おきに異なる2つのクロツクパルス
列で垂直シフトレジスタを駆動する形式のMOS
形イメージセンサにおいて、前記2つの駆動用ク
ロツクパルス列の一方のクロツクパルスの振幅を
他方のクロツクパルスの振幅に対して調整する振
幅調整回路を設けたことを特徴とするMOS形イ
メージセンサの出力レベル調整回路。
A MOS that drives a vertical shift register with two different clock pulse trains every other horizontal scan.
An output level adjustment circuit for a MOS type image sensor, characterized in that the output level adjustment circuit is provided for adjusting the amplitude of one clock pulse of the two driving clock pulse trains with respect to the amplitude of the other clock pulse. .
JP7698886U 1986-05-23 1986-05-23 Pending JPS62191267U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7698886U JPS62191267U (en) 1986-05-23 1986-05-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7698886U JPS62191267U (en) 1986-05-23 1986-05-23

Publications (1)

Publication Number Publication Date
JPS62191267U true JPS62191267U (en) 1987-12-05

Family

ID=30924576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7698886U Pending JPS62191267U (en) 1986-05-23 1986-05-23

Country Status (1)

Country Link
JP (1) JPS62191267U (en)

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