JPS6199886U - - Google Patents
Info
- Publication number
- JPS6199886U JPS6199886U JP1984184312U JP18431284U JPS6199886U JP S6199886 U JPS6199886 U JP S6199886U JP 1984184312 U JP1984184312 U JP 1984184312U JP 18431284 U JP18431284 U JP 18431284U JP S6199886 U JPS6199886 U JP S6199886U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- raster
- video signal
- image
- image video
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 2
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Image Generation (AREA)
- Studio Circuits (AREA)
Description
第１図はこの考案の一実施例の回路構成を示す
ブロツク図、第２図は第１図での各点における表
示を示す図、第３図は本実施例におけるタイムチ
ヤートを示す図、第４図は従来のＣＲＴ表示装置
の回路構成を示すブロツク図、第５図〜第８図は
第４図での各点における表示を示す図である。
１…イメージビデオ信号、２…論理積回路、３
，２２，２５…論理和回路、４…ＣＲＴモニタ、
５，１３，２１，３１…シフトレジスタ、６，２
３，２４，３２…フリツプフロツプ、１１…メモ
リ、１２…キヤラクタジエネレータ、１４…反転
回路。
FIG. 1 is a block diagram showing the circuit configuration of an embodiment of this invention, FIG. 2 is a diagram showing indications at each point in FIG. 1, FIG. 3 is a diagram showing a time chart in this embodiment, and FIG. FIG. 4 is a block diagram showing the circuit configuration of a conventional CRT display device, and FIGS. 5 to 8 are diagrams showing the display at each point in FIG. 4. 1... Image video signal, 2... AND circuit, 3
, 22, 25...OR circuit, 4...CRT monitor,
5, 13, 21, 31...shift register, 6, 2
3, 24, 32...Flip-flop, 11...Memory, 12...Character generator, 14...Inverting circuit.
Claims (1)
に供給して、前記メモリのデータに対応したキヤ
ラクタパターンとなる並列信号を得、該並列信号
をシフトレジスタに供給して直列信号に変換し、
該直列信号と外部より供給されたイメージビデオ
信号を重ねてＣＲＴモニタのスクリーン上に表示
する表示装置において、前記直列信号を１ラスタ
分遅延させる第１遅延回路と、該第１遅延回路で
１ラスタ分遅延した信号をさらに１ラスタ分遅延
させる第２遅延回路と、前記イメージビデオ信号
を制御するイメージビデオ信号制御回路とを具備
し、前記直列信号と、前記第１及び第２遅延回路
の各出力信号の論理和により前記イメージビデオ
信号制御回路を制御してキヤラクタ表示に隣接す
るイメージ表示部分を非表示にすることを特徴と
するイメージおよびキヤラクタの表示装置。 Supplying data from the memory to a character generator to obtain a parallel signal having a character pattern corresponding to the data in the memory, supplying the parallel signal to a shift register to convert it into a serial signal,
In a display device that superimposes the serial signal and an externally supplied image video signal and displays them on the screen of a CRT monitor, the first delay circuit delays the serial signal by one raster, and the first delay circuit delays the serial signal by one raster. a second delay circuit for further delaying the delayed signal by one raster, and an image video signal control circuit for controlling the image video signal, the serial signal and each output of the first and second delay circuits. An image and character display device, characterized in that the image video signal control circuit is controlled by a logical sum of signals to hide an image display portion adjacent to the character display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984184312U JPS6199886U (en) | 1984-12-06 | 1984-12-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984184312U JPS6199886U (en) | 1984-12-06 | 1984-12-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6199886U true JPS6199886U (en) | 1986-06-26 |
Family
ID=30741797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984184312U Pending JPS6199886U (en) | 1984-12-06 | 1984-12-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6199886U (en) |
-
1984
- 1984-12-06 JP JP1984184312U patent/JPS6199886U/ja active Pending
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