JPS6454488U - - Google Patents
Info
- Publication number
- JPS6454488U JPS6454488U JP14907687U JP14907687U JPS6454488U JP S6454488 U JPS6454488 U JP S6454488U JP 14907687 U JP14907687 U JP 14907687U JP 14907687 U JP14907687 U JP 14907687U JP S6454488 U JPS6454488 U JP S6454488U
- Authority
- JP
- Japan
- Prior art keywords
- pattern signal
- address
- adjustment
- brightness
- correction point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 1
Landscapes
- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
Description
第１図は本考案のデイジタルコンバーゼンス調
整用パターン信号発生回路に係る一実施例を示す
ブロツク図、第２図は第１図の各部の信号波形を
示す波形図、第３図は第１図の回路からのパター
ン信号によつて表示される画面状態の一実施例を
示す説明図、第４図は表示される画面状態の他の
実施例を示す説明図、第５図は従来のデイジタル
コンバーゼンス方式の構成を示すブロツク図、第
６図は第５図の装置によつて表示される補正点の
配置状態を示す説明図、第７図は従来のパターン
表示を説明する説明図である。
２４……クロスハツチパターン信号、２５……
アンド回路、２８……輝度切換回路、３０……切
換信号、３１……加算器、３２……調整用パター
ン信号。
FIG. 1 is a block diagram showing an embodiment of the digital convergence adjustment pattern signal generation circuit of the present invention, FIG. 2 is a waveform diagram showing signal waveforms of each part of FIG. 1, and FIG. An explanatory diagram showing one embodiment of a screen state displayed by a pattern signal from a circuit, FIG. 4 is an explanatory diagram showing another example of a screen state displayed, and FIG. 5 is a conventional digital convergence method. 6 is an explanatory diagram showing the arrangement of correction points displayed by the apparatus of FIG. 5, and FIG. 7 is an explanatory diagram illustrating the conventional pattern display. 24...Cross hatch pattern signal, 25...
AND circuit, 28... Brightness switching circuit, 30... Switching signal, 31... Adder, 32... Adjustment pattern signal.
Claims (1)
ルメモリのアドレスに同期してパターン信号を発
生するデイジタルコンバーゼンス調整用パターン
信号発生回路において、 前記デイジタルメモリのアドレスと調整中の補
正点のアドレスとに基づいて、調整中の補正点に
隣接する上、下、左、右の点若しくはこれらの点
の領域に対応した時間幅の輝度切換用パルスを発
生する輝度切換回路と、 前記パターン信号と前記輝度切換用パルスとに
基づいて、調整中の補正点の周辺のパターンに輝
度変化を与える調整用パターン信号を作成する回
路手段とを具備したことを特徴とするデイジタル
コンバーゼンス調整用パターン信号発生回路。[Claims for Utility Model Registration] In a pattern signal generation circuit for digital convergence adjustment that generates a pattern signal in synchronization with the address of a digital memory storing convergence correction data, the address of the digital memory and the address of the correction point being adjusted. a brightness switching circuit that generates a brightness switching pulse with a time width corresponding to the upper, lower, left, right points adjacent to the correction point being adjusted or the area of these points based on the pattern signal; A digital convergence adjustment pattern signal generation circuit, comprising circuit means for creating an adjustment pattern signal that changes the brightness of a pattern around a correction point under adjustment based on the brightness switching pulse. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14907687U JPS6454488U (en) | 1987-09-29 | 1987-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14907687U JPS6454488U (en) | 1987-09-29 | 1987-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6454488U true JPS6454488U (en) | 1989-04-04 |
Family
ID=31420976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14907687U Pending JPS6454488U (en) | 1987-09-29 | 1987-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6454488U (en) |
-
1987
- 1987-09-29 JP JP14907687U patent/JPS6454488U/ja active Pending
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