JPH0312297U

JPH0312297U -

Info

Publication number: JPH0312297U
Application number: JP6877490U
Authority: JP
Priority date: 1990-06-28
Filing date: 1990-06-28
Publication date: 1991-02-07
Anticipated expiration: 1998-12-23
Also published as: JPH0631506Y2

Description

[Brief explanation of drawings]

第１図は従来装置による表示画面の非反転およ
び反転の説明図、第２図は従来の表示制御回路の
構成例を示す図、第３図は第２図に示す回路の信
号タイミング図、第４図は本考案装置に基づく反
転表示画面の説明図、第５図は本考案装置の１実
施例の原理説明図、第６図は１実施例回路の構成
図、第７図は第６図に示す実施例回路の信号タイ
ミング図である。図中、１……ＣＲＴコントローラ、２……アト
リビユートメモリ、３……ドツトパターンメモリ
、４……並列−直列変換（Ｐ−Ｓ変換）回路、５
……ビデオコントロール回路、８……デコード回
路、９……水平タイミング回路、１０……フリツ
プフロツプ、１１乃至１４……ＡＮＤゲート、６
および１５……ＥＯＲゲートを示す。 FIG. 1 is an explanatory diagram of non-inversion and inversion of a display screen by a conventional device, FIG. 2 is a diagram showing a configuration example of a conventional display control circuit, FIG. 3 is a signal timing diagram of the circuit shown in FIG. 2, and FIG. 4 is an explanatory diagram of an inverted display screen based on the device of the present invention, FIG. 5 is an explanatory diagram of the principle of one embodiment of the device of the present invention, FIG. 6 is a block diagram of a circuit of one embodiment, and FIG. FIG. 3 is a signal timing diagram of the example circuit shown in FIG. In the figure, 1... CRT controller, 2... Attribute memory, 3... Dot pattern memory, 4... Parallel-serial conversion (P-S conversion) circuit, 5
...Video control circuit, 8...Decode circuit, 9...Horizontal timing circuit, 10...Flip-flop, 11 to 14...AND gate, 6
and 15... indicates an EOR gate.

Claims

[Scope of utility model registration request]

Controlled by memory addresses, horizontal and vertical synchronization signals, and display timing signals, there is a non-inverted display mode in which characters are displayed as bright spots within the screen display area excluding the periphery of the CRT screen, and an inverted display mode in which characters are displayed in black spots. and is capable of displaying character data in any one of the above two display modes, the CRT display device includes means for outputting the memory contents only during the period when the memory display timing signal is output, and means for outputting the memory contents in the reverse display mode. Inverted E
Vertical display is performed by inputting an OR means, a means for creating a horizontal display timing signal that extends the memory content display time before and after the horizontal synchronization signal, and a memory address decoding result to a flip-flop at a timing based on the horizontal synchronization signal. 1. A CRT display device comprising means for generating a timing signal, and simultaneously displaying a band-shaped inverted margin frame around the screen data display area when controlling the screen data display area to an inverted display mode.