JPS643892U - - Google Patents

Info

Publication number
JPS643892U
JPS643892U JP9331187U JP9331187U JPS643892U JP S643892 U JPS643892 U JP S643892U JP 9331187 U JP9331187 U JP 9331187U JP 9331187 U JP9331187 U JP 9331187U JP S643892 U JPS643892 U JP S643892U
Authority
JP
Japan
Prior art keywords
horizontal
scanning line
horizontal scanning
computer
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9331187U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9331187U priority Critical patent/JPS643892U/ja
Publication of JPS643892U publication Critical patent/JPS643892U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Image Generation (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図。
第4図は、従来装置のブロツク図である。第3図
は、単に4画素周期で処理した場合の水平線表示
例を示す図。第2図は、本考案により4画素周期
で処理した場合の水平線の表示例を示す図。 1:ホストCPU、2:インターフエース、3
:書込みアドレス作成回路、4:読み出しアドレ
ス作成回路、5:αデータ作成回路、8:YSレ
ジスタ、9:XSレジスタ、10:△Xレジスタ
、16〜19:レジスタ。
FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 4 is a block diagram of a conventional device. FIG. 3 is a diagram illustrating an example of horizontal line display when processing is performed simply at a four-pixel period. FIG. 2 is a diagram showing an example of a horizontal line displayed when processing is performed at a four-pixel period according to the present invention. 1: host CPU, 2: interface, 3
: Write address generation circuit, 4: Read address generation circuit, 5: α data generation circuit, 8: YS register, 9: XS register, 10: △X register, 16 to 19: registers.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 計算機により発生した輝度変調データをもとに
、そのデータをアナログ信号に変換しラスタスキ
ヤン形デイスプレイ装置に表示することで霧の模
擬を行なう計算機作像方式映像発生装置において
、輝度変調度カーブをあらかじめ計算しメモリに
記憶しておき、デイスプレイ装置の表示タイミン
グに同期してこのメモリから輝度変調度を読み出
しアナログ信号に変換するものであつて、水平線
と水平走査線が最初に交叉する水平走査線番号と
、その水平走査線上のX座標及び水平線の傾きを
記憶するレジスタを有し、各水平走査線ごとの水
平線のX座標を計算し、その座標値によりD/A
変換部への入力タイミングを制御することで、水
平線をなめらかに表示することを特徴とする計算
機作像方式映像発生装置。
In a computer-generated image generator that simulates fog by converting the data into an analog signal and displaying it on a raster scan type display device based on brightness modulation data generated by a computer, a brightness modulation degree curve is created in advance. It calculates and stores it in memory, reads out the luminance modulation degree from this memory in synchronization with the display timing of the display device, and converts it into an analog signal.The horizontal scanning line number where the horizontal line and horizontal scanning line intersect for the first time. It has a register that stores the X coordinate on the horizontal scanning line and the slope of the horizontal line, calculates the X coordinate of the horizontal line for each horizontal scanning line, and uses the coordinate value to determine the D/A.
A computer-generated image generation device characterized by displaying a horizontal line smoothly by controlling input timing to a conversion section.
JP9331187U 1987-06-19 1987-06-19 Pending JPS643892U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9331187U JPS643892U (en) 1987-06-19 1987-06-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9331187U JPS643892U (en) 1987-06-19 1987-06-19

Publications (1)

Publication Number Publication Date
JPS643892U true JPS643892U (en) 1989-01-11

Family

ID=31317757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9331187U Pending JPS643892U (en) 1987-06-19 1987-06-19

Country Status (1)

Country Link
JP (1) JPS643892U (en)

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