JPH0631506Y2 - CRT display device - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is intended to make it easier to see a reversed character or the like located at the boundary of the display area when the entire display area of the character or the like is displayed in reverse on a CRT display device. In addition, the present invention relates to a CRT display device in which an inversion margin frame is provided in contact with a boundary for displaying.

[Background of technology]

Conventionally, in the case of performing screen reverse display on a CRT display device, a method of reversing only a preset memory content display area has been adopted. Next, a specific example will be described.

FIG. 1 (a) exemplifies the display screen in the normal non-reverse display mode, and FIG. 1 (b) shows the same display screen in the reverse display mode. In the figure, the inside of the section indicated by the dotted line is the memory content display area S, and the outside is the blank area.

In Fig. 1 (a), the letters "A" and "B" are displayed as bright dots,
That is, it is a white display portion, and the rest of the background is a black display portion. On the other hand, in FIG. 1 (b), the remaining memory content display area S except for the characters "A" and "B" is all inverted to become a white display portion, and the characters "A", "B" and the blank area are Displayed in black.

In such a reverse display method, the black left vertical stroke of the character "B" is very close to the black margin area, and therefore is visually integrated and is difficult to see as a character. This is the other letters "D", "E", "F",
The same applies to "K" and the like. Generally, the character located at the boundary portion (dotted line position) of the memory content display area becomes larger or smaller, and such a difficult-to-see state occurs.

FIG. 2 shows a configuration example of a display control circuit according to the conventional screen reversal display method shown in FIGS. 1 (a) and 1 (b). In the figure, 1 is a CRT controller (CRTC), 2 is an attribute memory, 3 is a dot pattern memory, 4
Is a parallel-serial conversion (PS conversion) circuit, 5 is a video control circuit, 6 is an EOR gate, and 7 is an AND gate.

FIG. 3 is a timing chart of signals in portions indicated by through in the circuit of FIG. 2, and shows a state at the time of screen inversion.

The operation will be briefly described below with reference to FIGS. 2 and 3. The memory address for accessing the attribute memory 2 and the dot pattern memory 3 is a character address, and the dot pattern memory 3 is accessed by further superimposing the raster address. The parallel data format pattern data read from the dot pattern memory 3 is converted into serial data format data by the parallel-serial conversion circuit 4, and the video control circuit 5
It is controlled in accordance with the contents of the attribute together with the cursor signal, and is output as a video signal to a CRT circuit (not shown) via the EOR gate 6 and the AND gate 7.

In FIG. 3, a display timing signal is generated in the middle of the horizontal synchronizing signal. The display timing signal indicates a period in which data is read from the memory, and the data signal is output during this period.

The full screen reverse control signal is generated based on the command, and while this signal is "ON", the video signal is EO.
It is inverted in the R gate 6 and becomes an inverted video signal. This inverted video signal is gated by the display timing signal in the AND gate 7 and becomes an inverted video signal.

In this way, the inverted display period of the inverted video signal is determined by the period of the display timing signal, and the rising and falling edges of the display timing signal are timing-synchronized with the pattern data reading period from the memory. The screen reverse display as shown in FIG. 1 (b) is performed.

[Purpose and structure of device]

An object of the present invention is to provide a means for making it easy to see a reversed character located at the boundary of a reversed area in a screen reversed display in a conventional CRT display device, and has a CRT controller and a memory address output from the CRT controller. And controlled by raster address and horizontal / vertical sync signal, memory display timing signal,
There is a non-reverse display mode for displaying characters in bright dots and a full-screen reverse display mode for displaying characters in black dots in the screen display area excluding the peripheral portion of the CRT screen, and character data is either one of the above two display modes. In a CRT display device capable of displaying, a means for outputting the memory contents only while the memory display timing signal is being output, an EOR means for inverting the memory output in the full screen inversion display mode, and a horizontal memory based on the horizontal synchronizing signal. Means for creating a horizontal display timing signal that extends before and after the content display time, raster address of the raster that is earlier by a predetermined number of rasters than the first raster of the area for displaying the memory content, and memory address located during the blanking period of the raster and means for producing the decoded decoded output P ₁ to the final raster area for displaying the memory contents -Decode output P ₂ by decoding the raster address of the raster that is later than the specified number of rasters and the memory address located during the blanking period of the raster.
And the respective decode outputs (P ₁ , P ₂ ) are input to the flip-flop at the timing during the retrace time with the horizontal synchronizing signal as a reference, and are earlier than the first raster for displaying the memory contents by a predetermined raster number. Display the set and memory contents during the raster retrace period.Reset during the raster retrace period, which is later than the final raster by a predetermined number of rasters, to reset the vertical display timing signal that extends vertically before and after the memory contents display time. When the screen data display area is controlled in the full-screen reverse display mode, the output of the EOR means is cut out by the horizontal display timing signal and the vertical display timing signal to form a strip around the screen data display area. It is characterized by displaying an inversion margin frame.

[Example of device]

 The details of the present invention will be described below with reference to embodiments.

FIG. 4 is an example of a reverse display screen based on the device of the present invention, and a strip-shaped reverse margin frame area F shown by double diagonal lines is provided outside the memory content display area S shown in FIG. 1 (b). It is a thing. By displaying such a reverse margin frame,
It is possible to completely improve the state in which the reversed characters “A”, “B”, etc. located at the boundary of the memory content display area S become difficult to see.

FIG. 5 is an explanatory view of the principle of one embodiment for displaying the above-mentioned inversion margin frame.

FIG. 5 (a) schematically shows the inversion margin frame area in the screen address space. In the case of this embodiment,
The address space is composed of 102 characters in the horizontal direction and 787 in the vertical direction, and the memory content display area S is 8
It consists of 0 characters x 25 lines. The number of rasters for one line is 28. The size of the reverse margin frame is, for example, a width of one character on the left and right and a width of 12 rasters on the upper and lower sides.

The inversion margin frame area F set outside the memory content display area S is ₅ of F _{1 to} F ₅ as shown in (b) of FIG.
It is divided into two segments and is distributed in the address space as shown in Fig. 5 (a). However, since the address space is raster-scanned, the left and right sides and the upper and lower sides are connected. Therefore, by setting the start address of one frame to P ₁ ahead of the start position of F ₅ , and the end address to P ₂ after the end position of F ₃ , integration as shown in FIG. It is possible to display the highlighted inversion margin frame. The start address P ₁ and the end address P ₂ are each represented by a combination of a vertical raster address and a horizontal memory address. In order to detect these start address P ₁ and end address P ₂ , a decoder that inputs a raster address and a memory address is used, and the output thereof controls the start and end of the frame.

In the screen address space of FIG. 5 (a), the memory address is the memory display timing signal O in each raster.
These are continuously generated during the FF period, that is, the blanking period.

By the way, in order to secure display quality, it is desirable that the inversion margin frame area F is properly displayed from the left end of the screen. For that purpose, as shown in FIG. 5A, the start address P ₁ of one frame is on the top raster of the inversion margin frame segment F _{4 in} the upper part of the memory content display area S and in the horizontal display timing signal OFF period. That is, the operating time margin is set in the blanking period, and the end address P ₂ is set to the horizontal display timing signal OFF on the final raster of the reverse margin frame segment F ₃ at the bottom of the memory content display area S in the same manner. It may be set during the period.

In FIG. 5 (a), the hatched cross area is an area whose display is prohibited. Therefore, it is necessary to generate timing signals in the vertical and horizontal scanning periods so that the remaining areas of S and F _{1 to} F ₅ can be selected from the address space as the inverted display area. That is,
In the conventional method, it is sufficient to control so as to cut out the memory content display area S from the address space, and as described with reference to FIGS. 2 and 3, a relatively simple control circuit according to a single display timing signal. Could be realized by using.

However, according to the device of the present invention, it is necessary to display inversion margins of a predetermined width on the upper, lower, left and right sides of the memory content display area S. Therefore, display timing signals are provided separately vertically and horizontally.
It must be generated at such a timing as to prohibit only the cross-shaped region shown by the hatching in FIG.

FIG. 6 is a block diagram of an embodiment of a display control circuit capable of generating such vertical and horizontal display timing signals. The circuit of this embodiment is an improvement of the conventional circuit shown in FIG. In the figure, 1 is a CRT controller, 2 is an attribute memory, 3 is a dot pattern memory, 4
Is a parallel-serial conversion (PS conversion) circuit, 5 is a video control circuit, 8 is a decoding circuit, 9 is a horizontal timing circuit, 10 is a flip-flop, and 11 to 14 are AND circuits.
Gate, 15 is an EOR gate. The circuit elements with reference numbers 1 to 5 correspond to the circuit elements with the same numbers in FIG.

Further, FIG. 7 is a timing chart of signals in the portions shown in FIG. 6 indicated by'to ', and shows the state at the time of screen inversion.

The operation of the circuit of this embodiment will be described below with reference to FIGS. 5, 6, and 7.

Horizontal sync signal 'output from the CRT controller 1
The display timing signal 'is the same as that in the conventional circuit shown in FIG.

The display timing signal 'gates the output video signal of the video control circuit 5 in the AND gate 13 to generate a video signal'. The video signal 'is inverted in the EOR gate 15 to produce an inverted video signal' when the full screen reverse control signal 'is set to "ON". This inversion video signal'corresponds to the inversion video signal in FIG. 3, is all "ON" outside the memory content display period, and does not have the function of displaying the inversion margin frame. The full-screen reverse control signal 'is "OF
In the case of F ″, the video signal ′ is output from the EOR gate 15 as it is.

Therefore, the horizontal timing circuit 9 generates the horizontal display timing signal '. This signal 'has a pulse width extended by the left and right inversion margins before and after the display timing signal'.

The horizontal display timing signal 'is gated in the AND gate 14 together with the vertical display timing signal' which will be described later, and the inverted video signal 'is gated, the memory content display section and the inverted display frame section are cut out, and the inverted video signal' is output. Let

The vertical display timing signal 'is the flip-flop 10
Generated by. The flip-flop 10 is shown in FIG.
When the position P ₁ shown in (a) is scanned, it is set by the input applied to its J terminal, and when the position P ₂ is scanned, it is reset by the input applied to its K terminal.

As described with reference to FIG. 5, the decoding circuit 8 detects the P ₁ position and the P ₂ position based on the memory address and the raster address and outputs the decode signal ′ to the AN.
Apply to D-gates 11 and 12. At this time, the AND gates 11 and 12 are enabled by the signal 'supplied from the horizontal timing circuit 9, and the signal output from the decoding circuit 8 is the flip-flop 10.
And the flip-flop 10 is set or reset.

The section in which the enable signal 'is generated is the section surrounded by the chain lines g ₁ and g ₂ in FIG. 5 (a). Further, in the case of the interlace system, the decoding circuit 8 is configured so that it can detect two adjacent raster addresses in advance so that it can respond to any of the alternate interlaced scans.

As described above, the AND gate 14 outputs the inverted video signal 'when the display timing signal' is ON, that is, in the raster scanning the memory content display area S, and the display timing signal 'is OFF. At this time, that is, in the raster of the inversion margin frame areas above and below the memory content display area S, an inversion video signal such as'is output.

The horizontal timing circuit 9 is composed of, for example, a delay means such as a shift register and a logic gate, and generates a signal ',' having a required pulse width at a desired timing from the horizontal synchronizing signal '.

[Effect of device]

As described above, according to the present invention, when the display screen is displayed in full screen inversion, an inversion margin frame of a certain width is displayed outside the memory content display area, so that characters located at the edges are easy to see. Therefore, the reliability of reading the display data is improved and the work efficiency is improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of non-inversion and inversion of a display screen by a conventional device, FIG. 2 is a diagram showing a configuration example of a conventional display control circuit, FIG. 3 is a signal timing diagram of the circuit shown in FIG. FIG. 4 is an explanatory view of a reverse display screen based on the device of the present invention, 5
FIG. 6 is a diagram for explaining the principle of one embodiment of the device of the present invention, FIG. 6 is a configuration diagram of one embodiment circuit, and FIG. 7 is a signal timing diagram of the embodiment circuit shown in FIG. In the figure, 1 is a CRT controller, 2 is an attribute memory, 3 is a dot pattern memory, 4 is a parallel-serial conversion (PS conversion) circuit, 5 is a video control circuit, 8
Is a decoding circuit, 9 is a horizontal timing circuit, 10 is a flip-flop, 11 to 14 are AND gates, and 6 and 15 are EOR gates.

Claims (1)

[Scope of utility model registration request] 1. A CRT controller is provided, which is controlled by a memory address and a raster address output from the CRT controller, horizontal and vertical synchronization signals, and a memory display timing signal, and within a screen display area excluding the peripheral portion of the CRT screen. A memory display timing signal is output in a CRT display device that has a non-reverse display mode for displaying characters as bright dots and a full-screen reverse display mode for displaying characters as black dots and that can display character data in any one of the above two display modes. A means for outputting the memory contents only during a predetermined period, an EOR means for inverting the memory output in the full-screen inversion display mode, and a horizontal display timing signal which extends the horizontal memory contents display time before and after the horizontal synchronization signal as a reference. A means to create and a predetermined raster from the first raster of the area to display the memory contents And means for producing decoded the decoded output P ₁ memory address located in the blanking period of the raster address and the raster earlier raster by a few,
Means for decoding a raster address of a raster which is slower than the final raster of the area for displaying the memory contents by a predetermined number of rasters and a memory address located in the blanking period of the raster to generate a decode output P ₂ , and each decode output (P ₁ , P ₂ ) is input to the flip-flop at the timing during the blanking period with the horizontal sync signal as a reference, and the memory contents are displayed. It is equipped with a means to generate a vertical display timing signal that extends the front and back of the memory content display time in the vertical direction by resetting during the blanking period of the raster that is slower than the final raster by a predetermined number of rasters. When controlling the screen reverse display mode, the output of the EOR means is set to the horizontal display timing signal. And by cutting out by a vertical display timing signals, CRT display apparatus and displaying the strip-shaped inversion margin frame around said screen data display area.