JPS5843119B2 - Display control circuit for Go terminal device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an open base terminal device for playing games such as Souki using a television receiver. This relates to a control circuit for displaying images (in between).

For terminal devices that play games such as Souki using a television receiver, three levels of display are required: white okishi, black okishi, black base, and a neutral color between white and black (gray) for the background. become.

Furthermore, the pattern of the okishi must be displayed with the highest priority, and even if the okishi is white, it must be ensured that the foundations do not appear within it.

Such six-point control is an unnecessary function in character display devices that are already widely used.

Although there are graphic display devices that display neutral colors, these devices already store information regarding brightness in their refresh memory, so they require a large amount of memory and require a D-A converter for medium brightness. There was a flaw that made it necessary.

Moreover, in character display devices and graphic display devices, the screen is cleared and there is no need to display anything on the screen in the initial state.

Therefore, the contents of the refresh memory can be set to all zeros as an initial state, but in the case of four-base display, it is necessary to simply erase the okiishi and leave only the base eyes and background gray, and the conventional character The display control method of a display device or graphic display device cannot be directly adopted.

The present invention was made in view of the above circumstances, and when there is an okiishi, a black and white okiishi is displayed, where there is no okiishi and there is only a base pattern, a black background is displayed, and in other cases, a gray background is displayed. Moreover, it is an object of the present invention to provide a display control circuit for a four-unit terminal device in which a cursor for specifying a setting stone or a raising stone is displayed in black inside the white setting stone and in white in other places to provide an easy-to-read screen.

Hereinafter, the contents of the present invention will be explained in detail with reference to the drawings.

Figure 1 shows a method of displaying Go on a television receiver according to the present invention, with the background set at a brightness between white and black levels, the base board set to black, and the stones set according to their white and black levels. This indicates that the images are displayed at a white level and a black level, respectively.

Figure 2 shows an example of the configuration of the stone pattern, with the stones being 11 x 11.
This shows the case where the image is displayed using a pixel matrix.

As is well known, there are 525 scanning lines in the standard television system, but the composite synchronization signal is slightly modified from the standard system so that the first and second fields overlap to prevent flickering. This is commonly used in display devices using television receivers.

In this case, the effective number of scanning lines is about 240, taking into account the overscan of the television receiver.

Therefore, for example, in order to vertically line up 19 Okiishi pakun, only 11 to 12 scanning lines can be used for one pattern.

Incidentally, since an odd number is advantageous for aligning the center of the stone pattern with the line of the base, in FIG. 2, the stone is represented by a pixel matrix of 11×1.

In FIG. 2, the mark 1'' indicates pattern 1, and the area with no example indicates pattern 0.

Figure 3 is a block diagram of the stone slam generation circuit, and 301 is 13X1 in which each dot information shown in Figure 2 is stored.
A 3-bit read-only memory, 302 a read buffer register, 3030 to 303□.

is an address signal line. An external circuit (not shown) manages the stone pattern to be displayed at each time, and sets the address signal line 303 to "1" at the time when the first row of the stone pattern shown in FIG. 2 is to be displayed, for example.

As a result, the read-only memory 301 reads out the first row of okiishi pakun to the read buffer register 302.

A pixel clock generated in synchronization with the raster scan of the television receiver is applied to the register 302, and the stone pattern read out to the register 302 is sequentially sent out in accordance with the pixel clock.

The same holds true for the stone patterns in the second and subsequent rows.

It is sufficient to instruct the external circuit to determine whether the stone slam is white or black.

Figure 4 shows an example of the configuration of the base stitch, where the horizontal and vertical lines of the base stitch are Ho and Hl, respectively.
t..."HH3, Vo, Vl,-----V1
It is assumed that it exists at address position 8.

FIGS. 5a and 5b show an embodiment of the base pattern generation circuit.

In FIG. 5a, an H counter 501 is a counter that counts pixel clocks, and a counter 502 is a counter that counts carry pulses of the counter 501.

That is, the H counter 501 indicates the raster horizontal scanning position, and the V counter 502 indicates the vertical scanning position.

The contents of the H counter 501 are set to H.

Decoder 510o. H1 decoder 5100.・・・・・・
・By decoding each with the H18 decoder 51018, the horizontal addresses H6, Hl, etc.
・Signal will be issued when it corresponds to H18.

, hl, . . . hl8 are output. Similarly, the contents of the V counter 502 are set to V.

Decoder 520o, V. Decoder 5201.・・・・・・
- By decoding with the VI8 decoder 5201a, vertical addresses ■o, ■1.・・・・・・v18
signal V at the time corresponding to.

. ■1. ...■18 is output.

These. ,h,. ...hl8 and V.

, vl, . . . , Vl8, the base pattern shown in FIG. 4 can be created.

That is, as shown in FIG. 5, the signal V.

, ho is taken by an AND circuit 531, and a flip-flop 540 is set with its output to generate a signal V.

and hl8 in an AND circuit 532, and by resetting the flip-flop 540 with the output, the output of the flip-flop 540 is set to the address {circle around (2)} in FIG.
.

This will draw a horizontal line.

With a similar configuration, address ■0. ■2.・・・・・・
(1) 18 horizontal lines can also be generated.

Also, a signal.

, ho... By calculating the logical sum of hl8 in the OR circuit 550, the output of the OR circuit 550 is at address H8.
, Hl, . . . , a video signal that draws vertical lines of H18.

In the manner described above, the base pattern and the placing stone pattern can be generated independently.

Which setting stone pattern should be placed on which part of the base grid obtained in this way can be easily realized by preparing a refresh memory consisting of 19 x 19 memory cells with setting stone information in the same way as the character display. It is.

As for the okiishi pattern, an example is shown in Fig. 3 in which it is generated using a read-only memory, but the outputs of the H counter and V counter are decoded in the same way as the base pattern, and by combining the decoders, it can be generated using only a logic circuit. It is also possible to generate

FIG. 6 shows a cursor button generation circuit.

The cursor pattern is indicated by a vertical line spanning the top and bottom edges and a horizontal line spanning the left and right edges within the range where the background signal is output, and the intersection of these two is used to designate a setting stone, a raised stone, etc.

In FIG. 6, a cursor H address register 601 is a register that specifies the horizontal address position on the display surface of the cursor pattern, and a cursor (2) address register is a register that specifies the vertical address position.

- The number output circuit 603 outputs 1" when the contents of the H counter 501 that counts the pixel clock explained in FIG. If so, the logical product condition of the AND circuit 605 is taken, and a vertical cursor signal is sent out.

Similarly, the minus number output circuit 604 outputs "1" when the contents of the V counter 502 match the contents of the cursor address register 602, and outputs a horizontal cursor signal through the AND circuit 606 within the range where the background signal is output. Send out.

FIG. 7 shows an example of the overall configuration of a display control circuit according to the present invention.

In the figure, a background signal generation circuit 701 generates a background signal that defines the base in an actual Go game, and generates a signal at t'1 jj level in synchronization with a pixel clock belonging to a portion corresponding to the base. Occur.

The base-eye slam generation circuit 702 has a configuration as explained in FIG. 5, and generates a base-eye slam signal of the N I II level in synchronization with the pixel clock corresponding to the base eye.

The stone slam signal generation circuit 703 has the configuration described in FIG. 3, and outputs a stone slam signal that takes the level "1" at the pixel clock corresponding to the portion indicated by 1" in FIG. 2.

The black-and-white signal designation circuit 704 sends a "1" level signal to the black output signal line 704□ for the pixel clock for black stone display, and sends a "1" level signal to the white output signal line 7042 for the pixel clock for white stone display.
Output each level signal.

The cursor signal generation circuit 705 has a configuration as shown in FIG. 6, and outputs a "1" level signal in synchronization with the pixel clock forming the cursor pattern.

If a white stone slam signal is output through the AND gate 704', the AND gate 706 transmits it to the inverter 7.
This is a gate that prohibits the output of the base click signal based on the signal inverted at step 10.

The base eye slam signal passed through the AND gate 706, the black stone slam signal passed through the AND gate 703', and the cursor signal passed through the AND gate 718 are sent to the OR gate 70.
7, and the logical sum is taken at S.

In other words, each signal that displays black is collected in the OR game 1707.

The output of the OR gate 707 is a Nants gate 707 for inhibiting the black signal when the cursor needs to be displayed in white.
' and enters the AND gate 708, which is used to inhibit the background signal only in the case of black display.

Gate 709 is for signal waveform shaping and timing, and its output side is “1” when there is no black display.
” level (for example, +5V), and for black display, the level is “0” (for example, □V).

On the other hand, the white stone slam signal from the AND gate 704' passes through the AND gate 711, which prohibits the white signal from being generated when the cursor pattern is displayed in black, and passes through the OR gate γ1.
Enter 2.

The OR gate 712 performs the logical sum of the output signal of the AND gate 711 and the output signal from the AND gate 720 for displaying the cursor pattern in white, and inputs the result to the gate 713 .

Gate 713 is for signal waveform shaping and timing, similar to the previous gate 709, and its output side has a “1” level (+5■) if a white display is displayed, and a 10” level otherwise. (0) appears.

A resistor divider circuit 714 is connected to the output side of the gates 709 and 713.
is connected, and the voltage appearing at point 715 of its center tap is as follows.

White display Near 09 and 713 are both +5■, so +5V Black display: Points 709 and 713 are both O, so □V Intermediate display: Point 709 is +5■, point 713 is 0■, so the voltage at point 715 is between O■ and +5■ If the voltage is routed to an operational amplifier 716 with a high resistance feedback loop and summed with the composite synchronization signal,
A video signal is obtained at output terminal 117.

Note that the intermediate tone display level, that is, the background level, is determined by the position of the intermediate tap of the resistor divider circuit 714, so the brightness of the background can be adjusted by selecting this tap.

Among the cursor signals outputted from the cursor signal generating circuit γ05, those located inside the white stone are selected by the AND gate 718, and this output is led to the OR gate 101 and logically summed with the other black display signals.

At the same time, the output of AND gate 718 is connected to inverter 719
The signal is inverted at , and is led to the AND gate 711, thereby inhibiting the white display signal during this period.

In order to display white when the cursor is not within the white setting stone button, the output of the inverter 719 and the cursor signal are input to the AND gate 720 to create a white display cursor button, which is led to the OR gate 712 to display another white display. Performs a logical OR with the signal.

In this way, the board eye slam signal generation circuit 702, the stone slam signal generation circuit 703, and the cursor signal generation circuit 7
Even if 05 is operated completely independently, it is possible to avoid situations such as the foundation eye slam appearing in the white setting stone pattern, or the white cursor being overlapped with the white setting stone pattern so that the cursor cannot be seen.

The okishi can be displayed in white or black, the base grain is black, and the background is gray. Moreover, where the okishi is, there is no base grain or background, and where there is no okishi, the base grain is black, and the other The location can be displayed in gray.

The cursor is displayed with priority over all other objects, and white stones are displayed in black, and other areas are displayed in white, making it very easy to see.

Note that if the intermediate tap position of the resistor divider circuit 714 can be adjusted from the outside, the background level can be set according to preference.

This is effective for readjusting the level by moving the intermediate tap when the background brightness level changes depending on the ratio of white and black stones depending on the television receiver.

As explained above, according to the present invention, in a terminal device that uses a television receiver to play a game such as ``Saiji'', it is possible to independently create a board eye signal, a background signal for the background, and a stone slam signal. By passing only high-priority signals when these overlap in each pixel, the background has a brightness between white and black levels, the base is black, and the stones are at a level corresponding to white and black. screen configuration is possible.

Therefore, in order to initialize and create a state without any placing stones, it is only necessary to clear the placing stone slam signal, and the advantage is that the base and background can be easily left as they are.

In addition, since the level of the background neutral color can be changed with a simple resistor divider circuit, it is possible to prevent the intermediate color from becoming too close to the white or black level and making it difficult to see the stone due to differences in the gamma characteristics of television receivers. There are advantages.

Furthermore, the white part of the cursor is displayed in black, and the other parts are displayed in white, making it easy to see.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of the display of the surrounding base according to the present invention, Fig. 2 is a diagram showing an example of the configuration of the placing stone pattern, Fig. 3 is an example of the placing stone slam generation circuit, and Fig. 4 is a diagram showing the example of the placing stone slam generation circuit. Diagrams showing configuration examples, FIG. 5 is an embodiment of the base eye button generation circuit, FIG. 6 is an embodiment of the cursor button generation circuit, and FIG. 7 is an embodiment of the overall configuration of the display control circuit according to the present invention. It is. 701...Background signal generation circuit, 702...
・Base eye slam signal generation circuit, 703... Stone slam signal generation circuit, 704... Black and white signal designation circuit, 705
...Cursor signal generation circuit, 716...Operation amplifier.

Claims (1)

[Claims] 1. In a terminal device that uses a television receiver to play a game such as Souki, a first means for generating a base pattern, a second means for generating a pattern for black and white placing stones, and a second means for generating a pattern for placing stones or stones. a third means for generating a cursor pattern for specifying a stone, etc.;
Input the signal of the means of , and when there is a white setting stone pattern for each pixel of Rusk scan, it is at the white level, and there is a black setting stone slam, or when there is no white setting stone slam and there is a base pattern. is set to the black level, otherwise it is set to the intermediate level between white and black, and if there is a cursor pattern, if it is white level when there is no cursor pattern, it is forced to the black level, otherwise it is set to the black level. and a fourth means consisting of a group of logic circuits for controlling the video signal of the television receiver so as to forcibly set the video signal to a white level, and furthermore, the fourth means comprises a video signal at a level intermediate between white and black. A display control circuit comprising a resistor divider circuit with an intermediate tap for adjusting a signal.