JPS6319980A - Image display device - Google Patents

Abstract

PURPOSE:To obtain an image of high quality by a miniaturized circuit size by supplying an output obtained by adding the least significant bit of a digital video signal to its upper bit to one driving circuit out of a pair of field scanning driving circuits of a liquid crystal panel. CONSTITUTION:An analog video signal is inputted from a terminal Vin to an AD converter 4 and converted into a 4-bit digital signal. Upper three bits out of the four bits are inputted to input terminals A1-A3 of an adder 11 as they are and the least significant bit is inputted to an input terminal B3 through an AND gate 12. A vertical synchronizing signal every field scanning is inputted to a clock input of an FF ]4 and an output added by the least significant bit and an unadded output are alternately generated from the output of the adder 11 every field. The outputs are stored in a memory 7 through a gate buffer 15 and supplied to a pair of field scanning data side driving circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an image display device, such as a liquid crystal television, which uses a matrix type twisted nematic field effect liquid crystal panel and is capable of displaying halftones.

<Prior Art> Generally, in a device that displays an image using a liquid crystal display element in which an X electrode and a Y electrode are orthogonal to each other, for example, a television signal is received, and the analog signal is converted into a digital signal by an A-D converter. When converting and displaying an image, a 3-bit signal is handled for 8-gradation display, and a 4-bit signal is handled for 166-gradation display.

FIG. 4 is a block diagram showing a typical system configuration of a liquid crystal television receiver, and shows an example using a liquid crystal matrix panel with a vertically divided structure.

In this liquid crystal matrix panel with a vertically divided structure, the data-side column electrodes that cover the top half of the panel and the data-side column electrodes that cover the bottom half of the panel are arranged independently. A voltage waveform corresponding to image information is simultaneously applied from the top and bottom of the panel. Therefore, compared to a matrix panel that does not have a vertically divided structure, the scanning duty ratio is twice as high, and the contrast ratio of the screen can be improved.

Now, the television signal received from antenna L is R
The detected signal is output by the F unit 2 and introduced into the video amplifier 3. The output signal of the video amplifier 3 is converted into a 4-pin digital signal by the A-D converter 4, and the data-side drive circuits 5 and 6 of the upper and lower liquid crystal matrix panels 9a and 9b, respectively, Memory 7 having an area for storing data corresponding to the lower half
supplied to The scanning side drive circuit 8 is a circuit for simultaneously scanning the upper and lower halves of the liquid crystal matrix panel 9. While one half is scanning based on real-time data, the other half is scanning data stored in the memory 7. A scanning signal is output to perform scanning based on the following.

As the driving method, a method called a pulse width modulation method is adopted here, and the data side driving circuits 5 and 6 send voltage signals having a pulse width corresponding to the magnitude of the input digital signal to the liquid crystal matrix panel 9a.

9b. In general, the transmitted light intensity with respect to the applied voltage (effective value voltage) of a twisted nematic field effect liquid crystal element has a relationship as shown in Figure 7. In pulse voltage driving, the applied effective value voltage depends on the pulse width. Therefore, by changing the output pulse width, the intensity of light transmitted through the liquid crystal can be changed.

FIG. 5 shows an example of an actual signal processing circuit of a conventional device. A
The 4-bit output of the -D converter 4 is sent via a gate buffer 51 to the data storage area for the upper or lower half of the memory 7, and further via a buffer 52 to the data side drive circuit 5 or the data storage area for the upper or lower half. 6 is input. While the gate buffer 5I is receiving the video signal for one half, the data is read into the memory 7 and simultaneously supplied to the data side drive circuit for that half.
The contents of the memory 7 are supplied to the data side drive circuit for the other half.

FIG. 6 shows the relationship between the analog input signal to the A-D converter 4 and the 4-bit digital output. In this way, the analog video signal is converted into a 16-level digital signal, and therefore each liquid crystal element of the panel displays 166 gray levels.

<Problems to be Solved by the Invention> Incidentally, it goes without saying that the greater the number of gradations in a display, the better the image quality, but an increase in the number of bits that can be handled leads to an increase in the size of the liquid crystal drive circuit, and the circuit This is undesirable in terms of production and cost. In particular, when using a liquid crystal matrix panel with a vertically divided structure as described above, a frame memory is essential, so an increase in the number of bits increases the memory capacity, which is a major factor in increasing costs.

For example, in an 8-gradation display, the memory capacity may be 3 bits for the number of pixels, that is, three times the number of pixels, but in a 166-gradation display, it requires four times the number of pixels.

The present invention has been made in view of the above, and an object of the present invention is to provide an image display device capable of displaying gradations corresponding to the number of bits that is substantially one bit larger than the number of bits handled.

Means for Solving the Problems> The feature of the present invention is that, as shown in FIG. - An adder circuit 11 is provided for adding the least significant bit of the output of the D converter 4 to the upper bits excluding the least significant bit, and only when scanning one of a pair of fields forming a frame scan.
The present invention is configured to perform the above-mentioned addition, and the output of the adder circuit 11 is configured to be supplied to the data side drive circuit of the liquid crystal matrix panel.

In the example shown in Figure 1, the data-side drive circuit is supplied with a 3-bit digital signal having the relationship shown in Figure 3 with the video signal, so an 8-gradation display is actually possible. It will be done.

When the lowest bit of the output of the A-D converter 4 and the upper 3 bits excluding it are added, if the output of the A-D converter 4 is (0101), the 3-bit signal after addition is (01
1). If the above-mentioned addition is performed only during one field scan out of two field scans forming a frame scan, the output of the A-D converter 4 of (0101) will be The scanning line is (010)
, the odd-numbered scanning lines are displayed at gradations based on the three focus data of (011), and to the human eye, the overall appearance looks the same as the display at the intermediate gradation (0101), and in reality In general, it is possible to display gradations equivalent to those when handling 4 bits.

<Example> Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows an A-D converter 4 and each data side drive circuit 5 when the present invention is applied to a liquid crystal television receiver using a liquid crystal matrix panel with a vertically divided structure shown in FIG.
．． 6 is a diagram illustrating the configuration of a signal processing circuit between the two.

Of the 4-bit digital output of the A-D converter 4, the upper 3 bits are directly sent to the input terminal A of the adder 11.

~A, is input. The least significant bit of the 4-bit digital output is input to input terminal B of adder 11 via AND gate 12.

Input terminals B1 and B2 of the adder 11 are set to GND, that is, always set to 0.

The adder 11 has terminals Ai and B i (i=1.2.
3) and outputs it from the output terminal Ci, for example, AI = 1. AI = 0゜A3
= 1 and when B3 = 1, (101) + (001)
= (110) and calculate C+ =1. Cz =
1. Output Cs = 0.

In addition to the least significant bit output of the A-D converter 4 mentioned above, the outputs of the NAND gate 13 and the flip-flop 14 are input to the AND gate 12. All bit outputs of the A-D converter 4 are input to the NAND gate 13, and therefore, the input terminal of the adder 110B has the A-
An input signal of 1 is supplied only when the least significant bit of the output of the D converter 4 is 1, the output of the flip-flop 14 is H, and the output of the A-D converter 4 is not (1111). It turns out. That is, the relationship between the output of the AD converter 4 and the output of the adder 11 is as shown in [Table].

The reason for providing the NAND gate 13 is that when the output of the A-D converter 4 is (1111) and the addition is executed,
This is to prevent the output of the adder 11 from becoming (000), which would cause an inconvenience.

As shown in FIG. 2, the clock input of the flip-flop 14 is supplied with a vertical synchronizing signal (a) that is generated every field scan, and is a signal in which H/L is inverted every field scan. (b) is output and supplied to the AND gate 12. Therefore, the addition of the least significant bit to the most significant bit is performed every interval of field scanning, except in the case of (1111) described above.

The 3-bit output Ci of the adder 11 as described above is transmitted to the memory 7 corresponding to each half of the liquid crystal matrix panel 9.
area and the data side drive circuit 5 or 6, but in FIG. 1, only the circuit for one half is shown and the other half is omitted. Here, the gate buffer 15 is a circuit for passing the video data for the virtual half screen only when the data arrives, as shown in FIG. 2(C).
Alternatively, as shown in (d), it is opened and closed by a signal that is inverted at twice the period of field scanning. That is, while data for the corresponding one half is arriving, the data is supplied to the memory 7 for writing, and at the same time, the data is supplied to the data side drive circuit via the buffer 16 for real-time display.

Meanwhile, the gate buffer for the other half is closed, and the data written in the memory 7 during the previous field scan is read out and supplied to the data side drive circuit via the buffer. This point is equivalent to the circuit shown in FIG.

Next, the operation of the embodiment of the present invention will be explained. [Table] and 6th
From the figure, the relationship between the input voltage to the A-D converter 4 and the output of the adder 11 is as shown in FIG. Here, when the input terminal is vl, the output of the A-D converter 4 is (0101) from FIG. 6.

At this time, as is clear from FIG. 3, the output of the adder 11 is (011) in field scanning (1).

In field scanning (11), it becomes (010).

In other words, the liquid crystal matrix parameter 9 is 1. For example, the odd numbered scanning line is (011), and the even numbered scanning line is (010).
Since each field will be displayed based on 3-bit data, and one field scan is 60H2,
To the human eye, it looks the same as the display of the intermediate (0101") gradation. Note that the input voltage to the A-D converter 4 is V
2, the 4-bit output is (0100), but in this case, field scanning (1), (It)
In both cases, the output of the adder 11 is (010), and (010
0) is displayed.

As described above, in the memory 7° data side drive circuit 5.6 after the adder 11, although it is actually an 8-gradation display by handling 3-bit data, it is possible to display the intermediate tone of each gradation. It is also possible to display 155 gray scales.

In the above embodiments, a liquid crystal television with a memory using a liquid crystal matrix panel with a vertically divided structure was explained. Of course, the present invention can also be applied to liquid crystal televisions that display images in real time.

<Effects of the Invention> As explained above, according to the present invention, the lowest bit of the digital output is converted into the upper bit excluding the lowest bit and node at the subsequent stage of the A-D converter that digitizes the video signal. Since an adder is provided for adding A to
- When the D converter output is 4 bits, the number of bits handled is 3 bits, and 8 gradations are actually displayed, and 155 gradations including the intermediate tones can be displayed, so
This means that a display equivalent to 166 gradations can be achieved when the number of bits handled is 4 bits.

This means that the same display quality can be obtained by handling data with one bit fewer bits; for example, the shift register for data transfer in a liquid crystal drive circuit can now only use three columns instead of four columns. Therefore, the LSI scale can be reduced, the circuit scale can be reduced, and the cost can be reduced.

Further, in particular, in a liquid crystal television with a vertically divided structure, a significant reduction in memory can be achieved. That is,
Compared to the conventional device that displays 4-bit gradation, the present invention has 320 x 240 dot pixels;
The total capacity of the upper and lower parts can be reduced by 76.8 kb for a black and white TV, and 230.4 kb for a color TV.

[Brief explanation of drawings]

Fig. 1 is a circuit configuration diagram of the main part of the embodiment of the present invention, Fig. 2 is a time chart showing the operation of each part, and Fig. 3 is its A-D.
A graph showing the relationship between the input voltage to the converter 4 and the output code of the adder 11, Fig. 4 is a block diagram showing a typical configuration of a liquid crystal television receiver with an upper and lower split structure, and Fig. 5 shows a diagram of the conventional device. Main part circuit configuration diagram, Figure 6 is the 4th
Figure 7 is a graph showing the relationship between the input voltage to the A-D converter 4 and the output code of the A-D converter 4. This is a graph showing. 1...Antenna 2.-RF unit 3.-
Video amplifier 4...A-D converter 5.6--Data side drive circuit 7--Memory 8...-Scanning side drive circuit 9-Liquid crystal matrix panel 11--Adder 12--AND gate 13
---NAND gate 14--Flip-flop 15--Gate buffer 16--Buffer

Claims (1)

[Claims] Using a matrix-type twisted nematic field-effect liquid crystal panel, an analog video signal is converted into a digital signal of predetermined bits by an A-D converter, and the digital signal is supplied to the data side drive circuit of the liquid crystal panel to produce an image. In a device that performs display, an adder circuit for adding the least significant bit of the output of the A-D converter to the upper bits excluding the least significant bit is provided at a subsequent stage of the A-D converter to form frame scanning. An image display device characterized in that said addition is performed only during one of a pair of field scans, and the output of said adder circuit is supplied to said data-side drive circuit.