JPH0311473B2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention has a dot frame memory corresponding to each picture element, and has a dot frame memory corresponding to each picture element, and a plurality of bits or one bit per picture element.
This invention relates to a driving device for a dot matrix display panel such as a liquid crystal display that displays information in bits.

<Background of the Invention> An electronic device that has a television receiver using a dot matrix liquid crystal panel with an upper and lower split drive system, which has the added function of displaying not only television images but also characters such as text information, graphs, and games. has already been proposed.

In order to display television images on a liquid crystal panel with an upper and lower division drive method, a dot frame memory is required to temporarily store image information that is sequentially sent in real time. In addition, in order to obtain high-quality television image display, the amount of information stored in the frame memory must range from 8 to 16 tones per pixel.
Since it is necessary to display gradations, it is necessary to store at least 3 bits of information per pixel. On the other hand, when displaying characters such as letters and symbols, gradation is basically not required, so the amount of information per pixel is only 1 bit.

In other words, in such devices, the required frame memory capacity differs depending on whether the TV image is displayed or when the character display is performed, but with the conventional system, even when displaying the character In order to use the image display circuit as is, the information of 1 bit of 1 pixel is converted into completely white and completely black gradation data, and the frame memory of 3 bits of 1 pixel is used in the same way as when displaying TV images. It was used to display characters. Therefore, especially when displaying characters, more memory than necessary will be used.
This had the disadvantage of increasing power consumption.

I will now explain in more detail with reference to the drawings.

FIG. 1 shows an example of the circuit block of the entire television receiver described above. The entire equipment can be broadly divided into TV image signal source (3-bit signal source) 1,
Character display signal source (1-bit signal source) 2,
and a liquid crystal panel drive circuit 3.

For example, in the television image signal source 1, the video signal output from the RF unit 5 is transmitted to the video amplification circuit 9.
After passing through the A/D converter 10, the sampling pulse (PS) is used to generate the 3 pixels necessary for 8-gradation display.
It is converted into a bit digital signal. Further, a vertical synchronization signal V and a horizontal synchronization signal H are obtained by the synchronization separation circuit 8 and sent to the clock timing control circuit 23 through the VH changeover switch 21. Note that 4 is an antenna, 6 is an audio circuit, and 7 is a speaker.

Character signal source 2 is CPU11, ROM1
2. The RAM 13, I/O 14, video RM 15, etc. constitute a microcomputer system. For example, character information is generated by a microcomputer system here. Then, the CPU 11 operates according to the program written in the ROM 12, and the video RAM 15
Character information is written to. video
When the address of the RAM 16 is not accessed by the CPU 11, the address changeover switch 17 operates under the control of the CPU 11 and is connected to the video RAM scanning circuit 16. The video RAM scanning circuit 16 generates V and H signals equivalent to those for television signals, and in synchronization therewith, sequentially generates consecutive address signals. In response to these continuous address signals, the character information stored in the video RAM 15 is sequentially output to the parallel-serial conversion circuit 18, where it is converted into a sequential 1-bit signal and sent to the liquid crystal panel drive circuit 3.
given to.

The liquid crystal panel drive circuit 3 has the above two types of V,
H signal and two types of data signals are connected,
VH changeover switch 21, data changeover switch 22
3, which is switched by the external switch 19.
One of them is selected and input by the bit 1 bit switching signal SA. In synchronization with the V and H signals, the clock timing control circuit 23 generates various timing pulses necessary for driving the liquid crystal and sampling pulses (PS) necessary for obtaining television image data. On the other hand, in the liquid crystal panel 20 of the vertically split type, the data side electrode (X electrode) is divided into upper and lower halves so that the duty ratio is doubled in order to improve brightness or contrast. Furthermore, the scanning side electrode (Y electrode) is divided into upper and lower sections with n (for example,
30) Each electrode is connected in common to each other, and the whole is driven at a duty ratio of 1/n (1/30). In order to configure a television screen or a character screen on this liquid crystal panel 20, in order to send image signals sent in real time to the data side upper and lower electrodes X _A and X _B at different times,
A frame memory 25 is required to store all pixel information.

To explain this part in detail using the case of a TV image signal as an example, first of all, in the first half of one field,
The 3-bit signal containing the gradation signal sent in real time is transferred via the data branch circuit 24 to three sets of shift registers 26B in response to the clock signal φ. At the same time, the data is stored in three sets of frame memories 25B under the control of the memory selection signal _B and the write enable signal _B. On the other hand, the image information data of the previous field stored in the frame memory 25A is read out and transferred to the shift register 26A under the control of _{the A} and _A signals. In the second half of one field, the above operation is performed by exchanging A and B, and the 3-bit signal sent in real time is transferred to the shift register 26A, written to the frame memory 25A, and then transferred to the shift register 26A. 26
B has frame memory 25B in the first half of the field.
The image data stored in is transferred. That is, the real-time image and the stored image stored in the frame memory 25 are displayed on half the screen of the liquid crystal panel 20.
They will be displayed alternately.

The 3-bit image signal sent to the shift registers 26A and 26B is sent to the data latches 27A and 27B by the latch signal LS, which has one latch signal for every four H signals.
It is held in B. Then, one of the gradation display signals t ₁ to _{t 8} outputted from the gradation display circuit 28 is selected in the selection switch driver 29 based on the 3-bit data. These t ₁ to _{t 8} are pulse width modulation signals that determine eight gradations, and a driving voltage (voltage based on the so-called pulse width modulation method) is applied to the data side electrodes X _A and X _B based on this pulse width. It will be done. Also, in the scanning side drive circuit 30, the LS
The scanning side electrode (Y
A driving voltage is applied to the electrodes).

FIG. 2 is a block diagram embodying the main parts of the conventional system. The output of the character information signal source 2 is a 1-bit signal with a black and white display per pixel, whereas the output of the television image signal source 1 is a 3-bit signal with an 8-gradation display per pixel. Conventionally, when using 1-bit signal source 2, SA
Set the signal to “H” and set the data changeover switch 22.
By the function of AND circuit and OR circuit, frame memory 2
The input signals D ₁ , D ₂ , D ₃ to 5 were all connected to a 1-bit signal source 2 . Therefore, D ₁ , D ₂ , and D ₃ are all “H” or “L” and are “000” or “111”.
gradation is selected and displayed.

In FIG. 2, _{the A} and _B signals are A1, A2, A3, B1, and B1 of the frame memory 25, respectively.
This is a selection signal for B2 and B3. This signal is “H”
When , the memory is inactive and the memory data output becomes high impedance. Furthermore, _{the A} and _B signals are write enable signals. When the memory is in the operating state and _{the A} signal is “L”, the memory A1, A
2 and A3 enter the write state and store input signals D ₁ , D ₂ , and D ₃ , respectively. Also, at this time, the data output of the memory becomes high impedance. on the other hand,
When the memory is in operation and _{the A} signal is “H”,
Memories A1, A2, and A3 are in the read state,
The contents stored in memory are output.

First, in the first half of 1 field, _B is “L”,
WE _A becomes “H”. As a result, B1, B2, and B3 of the frame memory 25 enter the write state, and real-time data signals D ₁ , D ₂ , and D ₃ are stored.
On the other hand, the three-state buffer B of the data branch circuit 24 becomes conductive, and real-time data signals are sent to the D _01B , D _02B , and D _03B lines connected to the shift register 26B. Also, since _A is “H”,
A1, A2, and A3 of the frame memory 25 are in the read state, and the D _01A , D _02A , and D _03A lines connected to the shift register 26A have the memory A1, A
2. The data stored in A3 is sent. At this time, the 3-state buffer A of the data branch circuit 24
is in a non-conducting state, and the real-time data is D _01A , D _02A ,
It is not sent to the D _03A line. In the second half of the first field,
WE _B becomes “H”, _A becomes “L”, and the shift register 26B has frame memory B1, B2,
Real time data is sent to the output data of B3 and shift register 26A.

Therefore, in the conventional method shown in FIG.
Even in the case of a bit signal source, memories A1, A2, A
3, B1, B2, and B3 will operate. Semiconductor RAM used as memory has significantly different power consumption during operation and non-operation.
In CMOSRAM, the power consumption is 150mW during operation and about 5μW during non-operation, so the frame memory 25
The disadvantage of the conventional method of using extra power is that it consumes a lot of power.

<Object of the Invention> The present invention has been made in view of the above-mentioned points, and has devised a circuit for switching between a television image signal and a character information signal, and minimizes the frame memory used when displaying characters. , the purpose is to reduce excess power consumption.

<Embodiment> For example, in the case of a television receiver, the overall block diagram is as shown in FIG. 1, and the basic operation is also as described above. FIG. 3 shows a detailed block diagram of the main parts of the present invention.

An embodiment of the present invention will be described below with reference to FIG.

Set the SA signal to “H” and turn the data selector switch 2
If character information signal source (1-bit signal source) 2 is selected in step ₂ , A2, _A3 , B2,
B3 does not operate regardless of memory selection signals _A and _B , and only memories A1 and B1 operate.

First, in the first half of 1 field, _B is “L”,
WE _A becomes "H", memory B1 becomes a write state, and memory A1 becomes a read state. Furthermore, the three-state buffer B1' of the data branch circuit 24 becomes conductive, and real-time data _D1 is sent to the _D01B line. On the other hand, the 3-state buffer A1' is in a non-conductive state, and the output signal of the memory A1 is sent to the D _01A line. Also, since the SA signal is “H”, 3
State buffers A2' and B2' become non-conductive, and the D ₂ and D ₃ signal lines are separated from the D _02A , D _02B , D _03A , and D _03B lines. Then, the 3-state buffers A3 and B3 provided between the D _01A line and the D _02A and D _03A lines and between the D _01B and D _02B and D _03B lines become conductive, and the signals on the D _01A and D _01B lines become D _02A. , D _03A , and D _02B , D _03B lines. For this reason, shift registers 26A, 26
The signals sent to B are all "H" or all "L" depending on the signals D _01A and D _01B as in the conventional method.

In the latter half of one field, _B becomes "H" and _A becomes "L", and the output data of the frame memory B1 is sent to the shift register 26B, and the real time data _D1 is sent to the shift register 26A.

Note that in the case of a television image signal, the 3-state buffers A1', A2', and B of the data branch circuit 24
1' and B2' each operate as a pair and perform the same data branching operation as in the prior art. Furthermore, the 3-state buffers A3 and B3 become non-conductive when the SA signal becomes "L".

In this way, if the present invention is used, the memory A2,
Character display can be performed without operating A3, B2, and B3, and frame memory 2
It is possible to reduce the power consumption of 5.

<Effects of the Invention> As is clear from the above description, according to the present invention, the amount of information per pixel can be increased to a plurality of bits or The power consumption of a 1-bit selectable liquid crystal dot matrix display device can be reduced by not selectively operating an extra frame memory.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the entire television receiver, Figure 2
The figure is a detailed block diagram of main parts for explaining a conventional example, and FIG. 3 is a detailed block diagram of main parts for explaining an embodiment of the present invention. 1... Television image signal source, 2... Character display signal source, 3... Liquid crystal pulse drive circuit, 19...
...Signal source selection switch, 20...Liquid crystal panel, 2
2...Data changeover switch, 23...Clock timing control circuit, 24...Data branch circuit, 2
5... Frame memory, 26... Shift register, 27... Data latch, 29... Selection switch driver, 30... Scanning side drive circuit.

Claims (1)

[Scope of Claims] 1. A dot frame memory configured with a plurality of memory bits per picture element corresponding to each picture element, and each picture element of image information is stored as multi-tone information per picture element. Each pixel of character information is stored in a dot frame memory composed of a plurality of bits, each pixel of character information is stored in a structure of one bit per pixel of the dot frame memory, and the character information is stored in a dot frame memory in response to the selection of the character information source. The present invention is characterized in that the operation of the unnecessary dot frame memory in which the character information is not stored is prohibited, and the output signal of the dot frame memory in which the character information is stored is forced to be output to the output side of the unnecessary dot frame memory. A drive device for a dot matrix display panel.