JPH06118921A - Method and device for image information processing - Google Patents

Abstract

PURPOSE:To eliminate the need for an error frame memory which consists of a large number of bits and obtain a display image which is close to an original image by performing the carry adding process of the least significant digit bit of (L+1)-bit image data at intervals of two frames and generating L-bit corrected image data. CONSTITUTION:This processor consists of an in-frame process part 20, a signal generation part 21, an adding process part 22, and an image display data generation part 23. The in-frame process part 20 compresses 6-bit original image data into 4-bit internal process image data ID and outputs the data to the adding process part 22. Then the least significant digit bit of the 4-bit internal image process data ID generated by processing the original image data SD of an (N)th (N: natural number larger than two) frame in the frame is carried once to two frames and added to the high-order three bits of the internal image process data to obtain 3-bit correction data JD of the (N)th frame.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information processing method and an image processing apparatus, and more particularly, to an image display close to an original image by increasing the gradation display of an LCD display by a digital driver. The present invention relates to an image processing method and an image processing device.

[0002]

2. Description of the Related Art An image processing method according to a conventional example, especially L
As a method of displaying an image close to the original image by using a pseudo expression for the multi-gradation of a CD display, after the image information processing in the frame is performed by the inventor of the present invention,
A method for performing image information processing between frames has been proposed.

This method will be described below with reference to FIGS. 7 to 9. Here, only one color of red (R) will be described. The processing for green and blue is the same as that for red, and therefore will be omitted. The image information processing apparatus according to the conventional example is
It is provided between the output unit that outputs the original image data and the LCD driver that drives the LCD display.
This is a device for compressing bit original image data and outputting it as 3-bit image display data to a 3-bit input LCD driver.

As shown in FIG. 7, the conventional image information processing apparatus comprises an intra-frame processing section (10A) and an inter-frame processing section (10B). In-frame processing unit (10
A) comprises a first latch circuit (1), a first adder circuit (2), a first multiplexer (3), a second latch circuit (4) and a third latch circuit (5), The 6-bit original image data (SD) is compressed into 4-bit internally processed image data (ID) and output to the interframe processing unit (10B).

First, the function of each section of the intra-frame processing section (10A) will be described. First latch circuit (1)
Is the 6-bit original image data (SD) input to itself
Is output to the first adder circuit (2) in synchronization with the dot clock (DK). First adder circuit (2)
Is the original image data (SD) and the second latch circuit (4)
The 6-bit corrected image data (HD) is created by adding the in-frame error data (EI) read from the above, and is output to the first multiplexer (3).

The first multiplexer (3) divides the input 6-bit corrected image data (HD) into upper 4 bits and lower 2 bits, and the internal processed image data (ID) which is the upper 4 bits. Output to the third latch circuit (5) and the lower 2 bits are the intraframe error data (EI)
Is output to the second latch circuit (4). The second latch circuit (4) performs write / read processing of 2-bit intra-frame error data (EI), and synchronizes with the dot clock (DK) by the horizontal synchronization signal (He). In-frame error data (EI) for each pixel is held for one pixel.

The third latch circuit (5) receives the input 4
The bit internally processed image data (ID) is output to the second addition circuit (6) of the interframe processing unit (10B). Next, the interframe processing unit (10B) will be described. The inter-frame processing section (10B) is composed of a second adder circuit (6), a second multiplexer (7), an error data frame memory (8) and a fourth latch circuit (9), and receives 4 bits. Internally processed image data (ID)
Is output as 3-bit image display data (GD).

The second adder circuit (6) adds 4-bit internally processed image data (ID) and 1-bit inter-frame error data (EB) read from the error data frame memory (8). The resultant 4-bit correction data (JD) is output to the second multiplexer (7). The second multiplexer (7) divides the 4-bit correction data (JD) input from the second adder circuit (6) into upper 3 bits and lower 1 bit, and an image display of the upper 3 bits. The data (GD) is output to the fourth latch circuit (9), and the inter-frame error data (EB) which is the lower 1 bit of the correction data (JD) is written to the error data frame memory (8).

The error data frame memory (8) is for writing / reading out the inter-frame error data (EB) which is the lower 1 bit of the correction data (JD), and the inter-frame error data for each frame. (EB) is held for one frame period. The fourth latch circuit (9) is
This is a circuit for temporarily holding the image display data (GD) input from the second multiplexer (7) and outputting it to an external LCD driver (not shown) based on the dot clock (DK).

An image information processing method according to a conventional example will be described below, supplementing the operation of the apparatus. 8 and 9 are flowcharts illustrating an image information processing method according to a conventional example. In the following, the nth pixel of the Nth frame is defined as the [N, n] pixel.

First, step P in the flowchart of FIG.
1 is the first pixel of the first frame, the first [1,1]
[1,1] which is 6-bit data corresponding to the pixel of
The first 4 bits of the original image data (SD) are taken as the [1,1] internal image processing data (ID) corresponding to the [1,1] pixel, and the [1,1] original image The lower 2 bits of the data (SD) are held as the [1,1] in-frame error data corresponding to the [1,1] pixel.

At this time, the [1,1] th original image data is passed through the first latch circuit (1) to the first addition circuit (2).
Input to the first multiplexer (3). The first multiplexer (3) divides the [1,1] original image data into upper 4 bits and lower 2 bits, and the upper 4 bits are the [1,1] internal image processing data (ID). Is output to the third latch circuit (5), and the lower 2 bits are output to and held in the second latch circuit (4) as the [1,1] in-frame error data (EI).

Next, in step P2, the upper 3 bits of the [1,1] th internal image processing data (ID) are converted into the [1,
1] image display data (GD) corresponding to the [1] pixel, and the lower 1 bit is the [1,1] inter-frame error data (EB) corresponding to the [1,1] pixel. ). At this time, the 4-bit [1,1] internal image processing data (I) output from the third latch circuit (5) is output.
D) is output to the second multiplexer (7) via the second adder circuit (6), of which the upper 3 bits are the [1, 1] image display data and the fourth latch circuit (9). Is output to an LCD driver (not shown), and the lower 1 bit is the [1,1] inter-frame error data (E
B) is output to the error data frame memory (8) and held.

Then, in step P3, an initial condition of n = 2 is set. Next, in Step P4, the first
6-bit [1, n] original image data (SD) corresponding to the [1, n] pixel which is the nth pixel of the frame
And [1, n-1] corresponding to the [1, n-1] th frame.
−1] intra-frame error data is subjected to addition processing, and the [1, n] internal image processing data (ID) corresponding to the [1, n] pixel and the [1, n] frame The internal error data (EI) is generated.

At this time, the [1, n] th original image data is passed through the first latch circuit (1) to the first adder circuit (2).
Entered in. On the other hand, the [1, n−1] th inter-frame error data is read from the second latch circuit (4) based on the dot clock (DK). The first addition circuit (2) performs addition processing on the both to generate 6-bit data [1, n] corrected image data (HD) and outputs the data to the first multiplexer (3). . First
The (3) multiplexer (3) divides the [1, n] corrected image data (HD) into upper 4 bits and lower 2 bits, and the upper 4 bits are the [1, n] internal image processing data (ID). Is output to the third latch circuit (5), and the lower 2 bits are output to the second latch circuit (4) as [1, n] in-frame error data (EI).
Retained.

When the data output from the first adder circuit (2) becomes "0000XX" as a result of the carry by the addition process of the first adder circuit (2), the value is different from the original image data. Therefore, in such a case, 6-bit “111111” is output from the multiplexer (3) based on the carry signal output from the adder (2). Initially, since n = 2 due to the initial condition, in this step P4, the original image data (SD) corresponding to the [1,2] th pixel is input, and the internal image corresponding to the [1,2] th pixel is input. The processed data (ID) and the in-frame error data (EI) will be generated.

Then, in step P5, the upper 3 bits of the [1, n] th internal image processing data (ID) are taken,
The [1, n] th image display data corresponding to the [1, n] th pixel, the lower 1 bit is taken, and the [1, n] interframe error corresponding to the [1, n] th pixel is taken. Data (E
B). At this time, the [1, n] th internal image processing data (ID) output from the third latch circuit (5) is input to the second multiplexer (7) via the second adding circuit (6). To be done.

By the second multiplexer (7), the upper 3 bits of the [1, n] internal image processing data (ID) are used as the [1, n] image display data in the fourth latch circuit (9). Is output to an LCD driver (not shown), and the lower 1 bit is output to and held in the error data frame memory (8) as the [1, n] inter-frame error data (EB).

At first, since n = 2 according to the initial condition, in this step P5, the [1,2] th image display data (GD) and the [1,2] th interframe error data (E
B) will be generated. Next, in step P6,
Add 1 to n. Then, in Step P7, the first
A process for determining whether or not the frame process is completed is performed.
If the processing of the first frame is completed (Yes), the process proceeds to step P6, and if not completed (No), the process returns to step P4 and the processes of steps P4 and P5 are repeated.

By repeating the above process, the [1,3] th pixel, the [1,4] th pixel, ...
n] pixels, and image display data of all pixels in the first frame, intra-frame error data, and inter-frame error data are obtained. During this period, the intra-frame processing unit (10A) performs the so-called error diffusion method, and the inter-frame processing unit (10B) performs only the acquisition process of the inter-frame error data corresponding to each pixel for use in the subsequent inter-frame processing. Is going.

Next, step P in the flowchart of FIG.
In step 8, N = 2 and n = 1, that is, initial condition setting processing for frames and pixels is performed. Therefore, the subsequent processing is processing after the second frame. Then, step P9
Then, the [N, n] th original image data (SD), which is 6-bit data corresponding to the [N, n] th pixel, and the [N, nth]
[n-1] intra-frame error data (EI) is added, and then the [N, n] th internal image processing data (I
D) and the [N, n] th intra-frame error data (EI)
To generate.

At this time, the [N, n] th original image data (SD) is input to the first adder circuit (2) via the first latch circuit (1). On the other hand, the [N, n-1] th in-frame error data (EI) is read from the second latch circuit (4) based on the dot clock (DK). The first addition circuit (2) performs addition processing on the both to generate 6-bit [N, n] -corrected image data, and outputs the 6-bit [N, n] corrected image data to the first multiplexer (3). First
The (3) multiplexer (3) divides the [N, n] th corrected image data into upper 4 bits and lower 2 bits, and the upper 4 bits are the [N, n] internal image processing data (I
D) and is output to the third latch circuit (5). The lower 2 bits are the [N, n] th frame error data (E).
I) is output to the second latch circuit (4) and held.

If the data output from the first adder circuit (2) becomes "0000XX" as a result of the carry by the adder process of the first adder circuit (2), the value is different from the original image data. Therefore, in such a case, based on the carry signal output from the first adder circuit (2),
The first multiplexer (3) outputs 6-bit "1111".
11 "is output. At first, N is set according to the initial condition.
= 2 and n = 1, the original image data corresponding to the [2,1] th pixel is input, and the internal image processing data (ID) corresponding to the [2,1] th pixel and the intra-frame error data ( EI) will be generated.

Then, in step P10, the [N, n]
Internal image processing data (ID) and the [N-1, n] inter-frame error data (EB) are subjected to addition processing, and the [N, n] th pixel corresponding to the [N, n] th pixel The image display data (GD) and the [N, n] th inter-frame error data (EB) are generated. At this time, the 4-bit [N, n] internal image processing data (ID) output from the third latch circuit (5) is input to the second adding circuit (6), and at the same time, the error data frame memory From (8), 1-bit [N-1, n] inter-frame error data (E
B) is read and input to the second adder circuit (6). The second addition circuit (6) performs addition processing on the [N, n] th internal image processing data (ID) and the [N-1, n] th inter-frame error data (EB) to obtain 4 bits. [N, n] th correction data (JD) of
Is output to the multiplexer (7).

4 by the second multiplexer (7)
The upper 3 bits of the [N, n] th correction data (JD) of the bit are transferred to the LCD driver (not shown) via the fourth latch circuit (9) as the [N, n] image display data (GD). The low-order 1 bit is output to the error data frame memory (8) as the [N, n] th inter-frame error data (EB) and held.

In this step P10, the second
The result of carry by the addition processing of the addition circuit (6) of
The data output from the adder circuit (6) is “000X”
In this case, the 4-bit “1111” is output from the second multiplexer (7) based on the carry signal output from the second adder circuit (6). Is output.

Next, in step P11, 1 is added to n. Next, in Step P12, a determination process of whether or not the process of the Nth frame has been completed is performed. If the process of the Nth frame is completed (Yes), the process proceeds to step P13, and if not completed (No), the process is completed at step P9.
Then, the above process is repeated again.

Next, in step P14, an end confirmation process is performed, and if all the processes are completed (Yes), the process is completed, and if all the processes are not completed yet (No), the process returns to step P9 and again. The above process is repeated. By repeating the above process, the [2,1] th pixel, the [2,1] th pixel,
2] pixel, ..., [2, n] pixel ..., [3,1]
Pixel, [3,2] pixel, [3, n] pixel ...
[N, 1] th pixel, [N, 2] th pixel ...
[n] pixels ...
Image information processing can be performed for all frames after the th frame. During this period, the intra-frame processing unit (10A) performs a so-called error diffusion method, and the inter-frame processing unit (10B) outputs the inter-frame error data corresponding to each pixel to the pixel of the next frame, Addition processing is performed on the internal image processing data of pixels at the same position.

By the method as described above, the intra-frame error data (EI) of a certain pixel and the original image data (SD) of the adjacent pixel are subjected to an addition process to form the basis of the image display data (GD). Since the internal image processing data (ID) is generated, the difference in image display brightness between two adjacent pixels (for example, the [3,1] th pixel and the [3,2] th pixel) is small, and the image brightness depends on the position. Is smoothed, so-called pseudo contours can be prevented, and the inter-frame error data (EB) of a pixel and the internal image processing data (ID) of the pixel of the next frame at the same position as that pixel. Since the image display data (GD) is generated by performing addition processing of and, the multi-gradation is realized while stabilizing the image.

[0030]

However, according to the conventional method proposed by the inventor of the present invention, 1-bit interframe error data (EB) is stored in the error data frame memory (8) for 1 frame period. Since it must be held, if the number of pixels in one frame is M,
A memory that holds at least M bits of data is required. Since the number of pixels in one frame is enormous, a considerably large memory is required, and moreover, the data corresponding to the pixels must be sequentially read from the memory and processed, so that method is not easy either. It was

[0031]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional circumstances, and in order to perform display with a gradation number larger than the gradation number represented by L-bit image display data, L
An image information processing method for performing pseudo gradation processing on P-bit original image data larger than a bit, wherein (L + 1) -bit image data is created from the P-bit original image data,
By controlling whether the least significant bit of the (L + 1) -bit image data is added or not added to at least the upper bit of the (L + 1) -bit image data based on predetermined information, L bits This is solved by creating the corrected image display data of.

[0032]

[Operation] According to the first image information processing method of the present invention, an (L + 1) -bit image created by processing original image data of pixels of an N-th (N is a natural number of 2 or more) frame Based on the predetermined information, the least significant bit of the data is selected to be added or non-added to the upper L bits of the image data of at least (L + 1) bits, and the L-bit data that is the difference processing result is imaged. By outputting as display data, addition processing and non-addition processing are performed for each predetermined information.

That is, when the predetermined information is frame information, addition processing and non-addition processing are alternately performed for each frame. At this time, when the least significant bit of the (L + 1) -bit image data is “1”, the process of adding “1” and the process of adding “0” to the L-bit image data are framed. The error diffusion is performed for each frame. When the least significant bit is "0", the image data does not change even if the addition process and the non-addition process are alternately performed. Even in the case of a moving image, it is considered that adjacent frames are still images and the image data between frames is the same, which is 1-bit error data (L +
1) The error diffusion between frames can be realized by alternately performing the process of adding the least significant bit of the bit image data to the L-bit image data and the process of not adding it for each frame, and use of the error data frame memory Since it is equivalent to the above case, the error data frame memory having a huge number of bits, which was necessary in the past, becomes unnecessary.

Further, according to the second image information processing method of the present invention, in the first method of the present invention, (L +
1) Addition processing or non-addition processing of the least significant bit of bit image data to L bit image data is performed for each frame, line, and dot. For this reason,
It is possible to obtain a display image close to the original image while suppressing the flicker of the image as compared with the first method in which the flicker due to the brightness of the image is slightly observed by alternately performing the addition process and the non-addition process for each frame. Will be possible.

Further, according to the image information processing apparatus of the present invention, as shown in FIG. 2, it is provided with an in-frame processing means, a signal generating means, a gate means, and a computing means. For example, by the in-frame processing means, the Nth (N
Is a natural number of 2 or more), and original image data of pixels in a frame is processed in the frame to be (L + 1) -bit image data. Based on a control signal from the signal generating means, the gate means generates (L + 1) -bit image data. The least significant bit of the image data is output to the calculating means, and the calculating means (L + 1)
When the least significant bit of the bit image data is output, the least significant bit is added to the L bit image data to obtain the L bit image display data of the Nth frame, and the (L + 1) bit When the least significant bit of the image data is not output, the L-bit image data is output as it is as the L-bit image display data of the Nth frame. Therefore, the same effect as the output of the inter-frame error data (EB), which has been conventionally required to be added to the (L + 1) -bit image data, is produced, and thus the number of bits required conventionally is enormous. A memory for inter-frame error data is unnecessary.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image information processing apparatus and an image information processing method according to the present invention will be described in detail below with reference to the drawings. The image information processing apparatus according to the first embodiment of the present invention is provided between an output unit that outputs original image data and an LCD driver that drives an LCD display, and compresses 6-bit original image data. Then, the data is output to a 3-bit input LCD driver as 3-bit image display data.

The image information processing apparatus according to the first embodiment of the present invention, as shown in FIG.
0), a signal generator (21), an addition processor (22) and an image display data generator (23). The in-frame processing unit (20) includes a first latch circuit (20A), a first adder circuit (20B), a first multiplexer (20C),
The second latch circuit (20D) and the third latch circuit (2D
0E) and 4 bits of 6-bit original image data (SD)
The data is compressed into bit internally processed image data (ID) and output to the addition processing unit (22).

First, the function of each unit of the intra-frame processing unit (20) will be described. First latch circuit (20D)
Is the 6-bit original image data (SD) input to itself
Is output to the first adder circuit (20B) in synchronization with the dot clock (DK). The first addition circuit (20B) adds the original image data (SD) and the intra-frame error data (EI) read from the second latch circuit (20D) to obtain 6-bit corrected image data (H).
D) is created and output to the first multiplexer (20C).

The first multiplexer (20C) divides the input 6-bit corrected image data (HD) into upper 4 bits and lower 2 bits, and outputs the internally processed image data (ID) which is the upper 4 bits. Third latch circuit (20
It outputs to the second latch circuit (20D) the in-frame error data (EI) which is the lower 2 bits.

The second latch circuit (20D) performs writing / reading processing of 2-bit intra-frame error data (EI), and synchronizes with the horizontal synchronizing signal (He) to produce a frame for each pixel. The internal error data (EI) is held for one pixel. The third latch circuit (20E) outputs the input 4-bit internally processed image data (ID) to the second addition circuit (22A).

Next, the signal generator (21) will be described. The signal generator (21) includes a first flip-flop circuit (21A) and a second flip-flop circuit (21A).
B), third flip-flop circuit (21C), first
Of the exclusive OR circuit (hereinafter referred to as an XOR circuit) (21D) and the second XOR circuit (21E). Instead of the inter-frame error data (EB) of the conventional example, the internally processed image data is generated once for each frame. A signal for masking the least significant bit is output to the gate means (21F). The gate means (21F) carries the carry of the least significant bit once every two frames and outputs it to the addition processing section (22).

First flip-flop circuit (21A)
Is a circuit that divides the frequency of the dot clock (DK) and outputs it to the second XOR circuit (21E).
The flop circuit (21B) is a circuit that divides the horizontal synchronization signal (He) and outputs it to the first XOR circuit (21D). Also, a third flip-flop circuit (21C)
Is a circuit for dividing the vertical synchronizing signal (Ve) and outputting it to the first XOR circuit (21D).

The first XOR circuit (21D) takes the exclusive OR of the divided horizontal synchronizing signal (He) and vertical synchronizing signal (Ve) and outputs it to the second XOR circuit (21E). The second XOR circuit (21E) is a circuit, and the exclusive OR of the output signal from the first XOR circuit (21D) and the divided dot clock (DK)
This is a circuit for outputting to the gate (21F). Also, AND
The gate (21F) takes a logical product of the output signal from the second XOR circuit (21E) and the internally processed image data (ID) output from the intra-frame processing unit (20) to obtain 2
In one frame, data 0 is forcibly forced, and in the other frame, the least significant bit of the internal image processing data ID is carried to the second adder circuit (22A).

The addition processing section (22) is composed only of the second addition circuit (22A), and its function is to carry out internally processed image data which is carried out from the AND gate (21F) and is output once every two frames. The least significant bit of (ID) and the upper 3 bits of the internally processed image data (ID) output from the signal generator (21) are subjected to addition processing, and the resulting 3-bit correction data (JD) is obtained. The carry signal is output to the image display data generation unit (23).

The image display data generator (23) includes a second multiplexer (23A) and a fourth latch circuit (23).
B), and outputs the input 3-bit internally processed image data (ID) as 3-bit image display data (GD). At this time, a carry occurs as a result of the second addition processing, and when "000" is output, the original image data has a greatly different value, so the carry signal (car)
When ry) becomes "1", "111" is output by the second multiplexer.

The fourth latch circuit (23B) temporarily holds the image display data (GD) input from the second multiplexer (23A), and an external LCD driver (not shown) based on the dot clock (DK). It is a circuit for outputting to. As described above, the least significant bit is carried once in every two frames and is output to the addition processing unit.
The same effect as the output of the inter-frame error data to be added to the bit internal image processing data (ID) is achieved.
A memory for inter-frame error data having a huge number of bits, which is conventionally required, becomes unnecessary.

An image information processing method according to the first embodiment of the present invention will be described below, supplementing the operation of the apparatus. 4 and 5 are flowcharts for explaining the image information processing method according to this embodiment. In addition, in the following,
The nth pixel in the Nth frame is defined as the [N, n] pixel.

First, step P in the flow chart of FIG.
1 is the first pixel of the first frame, the first [1,1]
[1,1] which is 6-bit data corresponding to the pixel of
The first 4 bits of the original image data (SD) are taken as the [1,1] internal image processing data (ID) corresponding to the [1,1] pixel, and the [1,1] original image The lower 2 bits of the data (SD) are held as the [1,1] in-frame error data (EI) corresponding to the [1,1] pixel.

At this time, the [1,1] th original image data (SD) is input to the first adder circuit (20B) through the first latch circuit (20A), and is directly input to the first multiplexer (20C). ) Is output. The first multiplexer (20C) causes the [1,1] th original image data (S
D) is divided into upper 4 bits and lower 2 bits, and the upper 4
The bit is set as the [1,1] th internal image processing data (ID) and is output to the third latch circuit (20E).
Bits are the [1,1] intra-frame error data (EI)
Is output to and held in the second latch circuit (20D).

Next, in step P2, the upper 3 bits of the [1,1] th internal image processing data (ID) are changed to the [1,1,
1] image display data (GD) corresponding to the [1] pixel. At this time, the third latch circuit (20
The 4-bit [1,1] internal image processing data (ID) output from E) is output to the second multiplexer (23A) via the second addition circuit (20D), and the upper 3 Image display data with bit [1,1] (G
D) is output to an LCD driver (not shown) via the fourth latch circuit (23B).

Then, in step P3, an initial condition of n = 2 is set. Next, in Step P4, the first
6-bit [1, n] original image data (SD) corresponding to the [1, n] pixel which is the nth pixel of the frame
And [1, n-1] corresponding to the [1, n-1] th frame.
−1] intra-frame error data (EI) is added, and the [1, n] internal image processing data (ID) corresponding to the [1, n] pixel and the [1, n] ] In-frame error data (EI) is generated.

At this time, the [1, n] th original image data (SD) is input to the first adder circuit (20B) via the first latch circuit (20A). On the other hand, the [1, n-1] th in-frame error data (EI) is read from the second latch circuit (20D) based on the dot clock (DK). Both are added by the first adder circuit (20B), and the first [1,
[n] corrected image data (HD) is generated and output to the first multiplexer (20C). The first multiplexer (13) divides the [1, n] th corrected image data (HD) into upper 4 bits and lower 2 bits, and the upper 4 bits are the [1, n] internal image processing data (I
D) and output to the third latch circuit (20E),
The lower 2 bits are output to and held in the second latch circuit (20D) as the [1, n] in-frame error data (EI).

It is troublesome that the data output from the first addition circuit (20B) becomes "000000" as a result of the carry by the addition processing of the first addition circuit (20B). , 6-bit “111111” is output from the first multiplexer (20C) based on the carry signal output from the first adder circuit (20B).

At first, since n = 2 due to the initial condition, in this step P4, the original image data (SD) corresponding to the [1,2] th pixel is input and the [1,2] th pixel is inputted. The internal image processing data (ID) and the intra-frame error data (EI) corresponding to are generated. Next, in Step P5, the upper 3 bits of the [1, n] internal image processing data (ID) are taken to obtain the [1, n] image display data ((n) corresponding to the [1, n] pixel. GD).

At this time, the [1, n] th internal image processing data (I) output from the third latch circuit (20E).
D) is input to the second multiplexer (23A) via the second adding circuit (22A). The second multiplexer (23A) uses the upper 3 bits of the [1, n] internal image processing data (ID) as the [1, n] image display data (GD) to generate a fourth latch circuit (23B). Is output to an LCD driver (not shown) via.

At first, since n = 2 according to the initial condition, in this step P5, the [1,2] th image display data (GD) is generated. Next, step P6
Then, 1 is added to n. Then, in step P7,
A determination process of whether or not the process of the first frame has been completed is performed. When the processing of the first frame is completed (Yes),
When the process moves to step P6 and is not completed (No)
Returns to step P4 and repeats the processing of steps P4 and P5.

By repeating the above process, the [1,3] th pixel, the [1,4] th pixel ,.
n] pixels, and image display data (GD) and intra-frame error data (EI) of all pixels in the first frame are obtained. During this period, the intra-frame processing unit (2
0) uses the so-called error diffusion method. Next, in step P8 of the flowchart in FIG. 5, N = 2 and n = 1,
Initial frame and pixel condition setting processing is performed. Therefore, the subsequent processing is processing after the second frame.

Then, in step P9, the [N, n] th original image data (SD), which is 6-bit data corresponding to the [N, n] th pixel, and the [N, n-1] th pixel. After addition processing with the intra-frame error data (EI), the [N, n] th internal image processing data (ID) and the [N, n]
n] intra-frame error data (EI) is generated. At this time, the [N, n] th original image data (SD) is passed through the first latch circuit (20A) to the first addition circuit (20B).
Entered in. On the other hand, from the second latch circuit (20D), the [N, n-1] th intra-frame error data (EI)
Is read based on the dot clock (DK). The first addition circuit (20B) performs addition processing on the both, and 6-bit [N, n] -th corrected image data (HD)
Is generated and output to the first multiplexer (20C). The first multiplexer (20C) divides the [N, n] th corrected image data (HD) into upper 4 bits and lower 2 bits, and the upper 4 bits are the [N, n].
Internal image processing data (ID) and output to the third latch circuit (20E). The lower 2 bits are the [N, n]
In-frame error data (EI) is output to and held in the second latch circuit (20D).

It is troublesome that the data output from the first addition circuit (20B) becomes "000000" as a result of the carry by the addition processing of the first addition circuit (20B). , 6-bit “111111” is output from the first multiplexer (20C) based on the carry signal output from the first adder circuit (20B). Initially, N = 2 and n = 1 depending on initial conditions.
Therefore, the original image data (SD) corresponding to the [2,1] pixel is input, and the internal image processing data (ID) and the intra-frame error data (EI) corresponding to the [2,1] pixel are input. Will be generated.

Then, in step P10, the least significant bit of the internal image processing data (ID) is the signal generation unit (21).
Masked by "1" or "0" output from
Carry once to the frame and add the second adder circuit (22A)
Is output to. Next, at step 11, the upper 3 bits of the [N, n] th internal image processing data (ID) are added.

In this step P11, the second
Result of carry by addition processing of the addition circuit (22A) of
The data output from the second addition circuit (22A) is "0".
In such a case, 3 bits "111" are output from the second multiplexer (23A) based on the carry signal output from the second adder circuit (22A). .

Here, the signals generated by the signal generator (21) will be described with reference to the timing chart of FIG. The signal generator (21) first supplies the dot clock (DK) to the first flip-flop circuit (21A) and the second flip-flop circuit (21A).
The horizontal synchronizing signal (He) is input to B) and the vertical synchronizing signal (Ve) is input to the third flip-flop circuit (21C), respectively, and the frequency is divided. Vertical divided frequency signal (V
e) and the horizontal synchronizing signal (He) are output to the first XOR circuit (21D), and the first XOR circuit (21D) is output.
The non-exclusive OR is taken by and the result is the second XO
It is output to the R circuit (21E).

On the other hand, the divided dot clock (DK)
Is output to the second XOR circuit (21E), and the second XOR circuit (21E) outputs the first XOR circuit (21E).
D) output signal and divided dot clock (D
K) and the AND gate (21
It is output to F). At this time, the signal output to the AND gate (21F) has a signal waveform having a relationship as shown in the timing chart of FIG. 6, and first, the non-exclusive logic of the vertical synchronizing signal (Ve) and the horizontal synchronizing signal (He). This is a signal that is inverted for each dot, each line, and each frame by taking the non-exclusive logical sum of the sum and the vertical synchronization signal (Ve). The reason why such a signal is generated will be described in detail later.

Next, returning to the flow chart of FIG.
Continue the explanation. Next, in Step P12, the [N, n] -th
3 bits of the correction data (JD) of No. 1 is output as the [N, n] th image display data (GD). At this time, the second
[N, n] th correction data (JD) output from the adder circuit (22A) of the second multiplexer (23A)
After being subjected to carry processing, 3 bits are output to the fourth latch circuit (23B) as the [N, n] th image display data (GD). Next, based on the dot clock (DK), the [N, n] th image display data (GD) is output from the fourth latch circuit (23B).

Next, in step P13, 1 is added to n. Next, in Step P14, a determination process as to whether or not the process for the Nth frame is completed is performed. If the process of the Nth frame is completed (Yes), the process proceeds to step P15, and if not completed (No), the process goes to step P9.
Then, the process of steps P9 to P13 is repeated again.

Next, in step P15, 1 is added to N. By repeating the above processing in this way,
1] pixel, [2,2] pixel, ..., [2, n] pixel, ..., [3,1] pixel, [3,2] pixel, [3, n] Pixel, [N, 1] pixel, [N, 1] pixel
2] pixels, [N, n] th pixel, and so on can be sequentially processed, and image information processing can be performed for all frames after the second. During this period, the in-frame processing unit (20) performs a so-called error diffusion method.

Next, in step P16, an end confirmation process is performed, and if all the processes are completed (Yes), all the processes are completed, and all the processes are not yet completed (No).
Returns to step P9 and repeats the above processing again. As described above, according to the image information processing method according to the embodiment of the present invention, the original image data (SD) of the pixel of the N-th (N is a natural number of 2 or more) frame is processed in the frame and created. The least significant bit of the generated 4-bit internal image processing data (ID) is carried once in every two frames, and is added to the upper three bits of the internal image processing data (ID) to perform the addition processing of the three bits of the Nth frame. The correction data (JD) is used.

For this reason, the error data frame memory having a huge number of bits, which has been conventionally required, is unnecessary for the following reasons. That is, the display image can be considered as a still image if it is captured by two adjacent frames, and the original image data (SD) is output with almost no change. Therefore, in the method of the conventional example, the internal image processing data (I
When the processing of adding 1-bit inter-frame error data to D), the following relationship is obtained.

[0069]

[Table 1]

Here, focusing on the inter-frame error data to be added to the next frame, for each frame,
"1", "0", "1", "0", ... Are repeatedly output. If this and the least significant bit are added, a carry will occur once every two frames.

Therefore, in such a case, even if the inter-frame error data is not calculated, the least significant bit is carried to the upper 3 bits of the internal image processing data (ID) alternately for each frame and the addition processing is performed. By doing so, it is the same as reading the inter-frame error data (EB) from the error data frame memory and performing addition processing. Therefore, by outputting such a signal, the error data frame memory having a huge number of bits, which has been conventionally required, becomes unnecessary.

However, simply "1" for each frame,
When "0", "1", and "0" are added, the frame to which "1" is added becomes bright and the frame to which "0" is added becomes dark. If the light-dark reversal is repeated for each frame, it will be recognized as an image flicker. Therefore, the first in the first frame
, "0" is added to the second line, "1" is added to the third line, and so on. Attempts have been made to average the luminance of each frame by adding either "1" or "0".

However, even if the process of adding either "1" or "0" alternately is performed for each line, the LCD
When the driver performs line inversion drive, the LCD drive voltage of the line to which "1" is added shifts to the higher side, and a DC component appears, causing burn-in of the LCD display, and LCD drive. Cause trouble.

Therefore, "1" is added to the first pixel, "0" is added to the second pixel, "1" is added to the third pixel, and so on. By alternately adding either "1" or "0", it is possible to prevent the driving voltage of the LCD of the line to which "1" is added from being shifted to a higher one, and to suppress the direct current of the driving voltage. It becomes possible to cut the ingredients.

Therefore, the signal generating section outputs a signal inverted for each frame, each line, and each dot, thereby preventing the flicker of an image and the appearance of a DC component in the driving voltage of the LCD, and the conventional example. Thus, it is possible to obtain the same effect as that when the inter-frame error data is read from the error data frame memory and added. In the present embodiment, the intra-frame processing unit (20) is an example of the intra-frame processing unit, the signal generation unit (21) is an example of the signal generation unit, and the addition processing unit (22) is an example of the addition unit. The image display data generation unit (23) is used as an example of the calculating means, and the internal image processing data (ID) is used as an example of the (L + 1) -bit image data.
The correction data (JD) is used as an example of the (L + 1) -bit corrected image data, but the configuration of the present invention is not limited thereto.

In this embodiment, the image information processing apparatus of 6-bit input and 3-bit output is explained.
The number of input / output data bits to which the present invention can be applied is not limited thereto, and is applicable to, for example, an 8-bit input-3 bit output image information processing device, an 8-bit input-4 bit output image information processing device, and the like. .

[0077]

As described above, according to the first and second image information processing methods of the present invention, the original image data of the pixels of the N-th (N is a natural number of 2 or more) frame is stored in the frame. The least significant bit of the (L + 1) -bit image data created by processing is carry-added every two frames,
L-bit corrected image data is created.

Therefore, the inter-frame error diffusion process eliminates the need for an error data frame memory having a huge number of bits, which has been conventionally required. Further, according to the third image information processing method of the present invention, in the first method of the present invention, the process of carrying the least significant bit of the (L + 1) -bit image data is performed for each frame by line. For each dot, "1" and "0" are added alternately.

Therefore, compared to the first method, it is possible to obtain a display image close to the original image while suppressing the flicker of the image.

[Brief description of drawings]

FIG. 1 is a flowchart illustrating an image information processing method according to the present invention.

FIG. 2 is a principle diagram of an image information processing apparatus according to the present invention.

FIG. 3 is a configuration diagram of an image information processing apparatus according to an embodiment of the present invention.

FIG. 4 is a first flowchart illustrating an image information processing method according to an embodiment of the present invention.

FIG. 5 is a second flowchart illustrating an image information processing method according to an embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the signal generator according to the embodiment of the present invention.

FIG. 7 is a configuration diagram of an image information processing apparatus according to a conventional example.

FIG. 8 illustrates a first example of an image information processing method according to a conventional example.
It is a flowchart of.

FIG. 9 is a second diagram for explaining the image information processing method according to the conventional example.
It is a flowchart of.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kazuhiko Moriwaki 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (72) Inventor Makoto Shimizu 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Denki Co., Ltd. (72) Inventor Hisao Uehara 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (8)

[Claims] 1. An image information processing method for performing pseudo gradation processing of P-bit original image data larger than L bits in order to display a gradation number larger than that represented by L-bit image display data. In addition, (L + 1) -bit image data is created from the P-bit original image data, and the least significant bit of the (L + 1) -bit image data is added to at least the upper bit of the (L + 1) -bit image data. An image information processing method, characterized in that L-bit corrected image display data is created by controlling whether to perform processing or non-addition processing based on predetermined information. 2. The predetermined information is frame information including the P-bit original image data, and the addition processing and the non-addition processing are alternately selected for each frame. Image information processing method. 3. The predetermined information relates to frame information including the P-bit original image data, line information, and dot information, and the addition process and the non-addition process are alternately performed for each frame, each line, and each dot. The image information processing method according to claim 1, wherein the image information processing method is selected. 4. From the P-bit original image data, (L +
1) The process of creating bit image data is characterized by an error diffusion method in which lower P- (L + 1) bits of P bit image data are diffused as error data to other pixels in the same frame. The image information processing method according to claim 1. 5. An image information processing apparatus for performing pseudo gradation processing of P-bit original image data larger than L bits in order to display a gradation number larger than that represented by L-bit image display data. A first processing means for creating (L + 1) -bit image data from the P-bit original image data; a signal generating means for generating a control signal based on predetermined information; And (L + 1) gate means for controlling the transmission of the least significant bit of the (L + 1) -bit image data.
At least the upper L bits of the image data of bits and the output of the gate means are applied, and an arithmetic means for outputting the image display data of L bits is provided, and the image data of the first (L + 1) bits based on the predetermined information. The image information processing apparatus, wherein the least significant bit of is selected by the arithmetic means to be added or not added. 6. The image information processing apparatus according to claim 5, wherein the signal generating means generates the control signal that alternates for each frame based on a signal synchronized with the frame. 7. The signal generating means generates the control signal that alternates dot by dot, line by line and frame by frame based on a signal synchronized with a frame, a signal synchronized with a horizontal line and a signal synchronized with a dot. The image information processing apparatus according to claim 5, wherein: 8. The error diffusion processing means for diffusing the lower P- (L + 1) bits of the P-bit original image as error data to other pixels in the same frame. The image information processing apparatus according to claim 5, which is characterized in that.