JPH03118596A - Gradation display control system - Google Patents

Abstract

PURPOSE:To reduce crosstalk and to improve display quality by constituting one picture element of a matrix display panel with plural display cells, and performing gradation control by combining picture element area modulation control and frame modulation control. CONSTITUTION:One picture element 2 in the matrix display panel 1 constituting the display cell 3 at the intersection of a data electrode 4 and a scan electrode 5 is composed of the plural display cells 3. The picture element area modulation control to set a lighting state by selecting the display cell of one picture element 2 according to gradation display data is performed. Also, the frame modulation control to set only one display cell out of the plural display cells 3 in one picture element 2 at the lighting state or delighting state in frame unit is performed, and also, such control to change sequentially the position of one display cell which performs the frame modulation control in the picture element 2 in a direction of the data electrode 4 is performed. Thereby, the number of times of inversion of data in the direction of the data electrode 4 can be uniformized, and flicker can be prevented from occurring, and also, the crosstalk can be reduced.

Description

[Detailed Description of the Invention] [Summary] Reducing crosstalk regarding a gradation display control method in which one pixel is configured with a plurality of display cells and is controlled by a pixel area modulation method and a frame modulation method to display gradation. With the aim of improving display quality, one pixel of a matrix display panel in which a display cell is formed at the intersection of a data electrode and a scanning electrode is formed by a plurality of the display cells, and the plurality of display cells In a gradation display control method that performs gradation display by selection control, pixel area modulation control is performed to select a display cell within one pixel and turn it on in accordance with gradation display data, and performs frame modulation control to turn only one display cell out of a plurality of display cells into a lit or non-lit state on a frame-by-frame basis, and performs frame modulation control within pixels arranged in a direction along the data electrode. The configuration is such that control is performed by sequentially changing the position of one display cell.

[Industrial Field of Application] The present invention relates to a gradation display control method in which one pixel is configured by a plurality of display cells and is controlled by a pixel area modulation method and a frame modulation method to perform gradation display.

Matrix display panels have display cells formed at the intersections of multiple data electrodes and scan electrodes arranged orthogonally to each other, and are used in various display devices because they are thin and lightweight. . In particular, matrix display panels using STN liquid crystals can be driven at low voltages.
In addition, since the contrast can be relatively high, it is widely used as a display device for portable devices.

However, the matrix type display panel as mentioned above is lit (on). Since a configuration that displays two non-lit (off) pixels is common, when displaying halftones, it is driven by a control method such as a frame modulation method or a pixel area modulation method. It is desired to improve the display quality when performing such gradation display.

[Prior Art] In a matrix display panel in which a plurality of data electrodes and a plurality of scan electrodes are orthogonally arranged with a liquid crystal interposed therebetween, the scan electrodes are sequentially selected, a scan voltage is applied, and the scan voltage is applied in synchronization with the selected scan electrodes. Applying a data voltage according to the displayed data to the data electrode,
It controls the transmittance so that it corresponds to the effective voltage of the display cell, and displays images and the like.

As mentioned above, such a matrix display panel is
Since each display cell is generally configured to display two cells, one lit (ON) and one non-lit (OFF), the following methods are conventionally known for displaying halftones.

(a) A voltage modulation method that performs gradation display by setting the voltage applied to nine display cells to a value between the lighting voltage and the non-lighting voltage.

b) A pulse width modulation method that controls the pulse width of the applied voltage so that it has a value between the lighting voltage and the non-lighting voltage in zero equivalent terms.

(C) A frame modulation method that controls the number of lit cells for each frame.

(d) A pixel area modulation method in which one pixel is composed of a plurality of display cells and the number of lit cells in the pixel is controlled.

The above voltage modulation method (a) cannot use a normal binary output driver, but requires a multi-value output driver that can output any value of voltage between the lighting voltage and the non-lighting voltage. Therefore, there is a drawback that the cost increases. or(
Since the pulse width modulation method b) controls the pulse width of the applied voltage according to the gradation display data, it has the disadvantage that timing control is complicated.

In addition, the frame modulation method (C) switches lit (on) cells between multiple frames, for example, OFF for 3 frames, OFF for 2 frames, OFF for 1 frame, and OFF for 3 frames. By turning it on for one period, four gradations can be obtained, and timing control is relatively easy. In the pixel area modulation method (d), one pixel is configured with a plurality of display cells and the number of lit (on) cells is controlled. For example, if one pixel is configured with three display cells, three display cells are displayed. By turning off the cell, turning off 2 display cells, turning 1 display cell off, and turning on 3 display cells, 4 gradations can be obtained.
Although the number of drivers increases, a binary output driver can be used. Furthermore, the number of gradations can be increased by combining the frame modulation method (C) and the pixel area modulation method (d).

[Problem that the invention seeks to solve]

A gradation display control method that combines a frame modulation method (C) and a pixel area modulation method (d) is considered to be promising because it has the advantage of being able to utilize current integrated circuit drivers. However, there are problems with crosstalk and flicker. That is, in the frame modulation method, the cycle in which lighting and non-lighting are repeated between a plurality of frames becomes longer as compared to the frame cycle as the number of lighting cycles decreases, and this is visually recognized as flicker.

Furthermore, when displaying a pattern in which lighting and non-lighting are alternately repeated along the data electrodes of a matrix display panel, the voltage waveform applied to the display cells becomes dull and the effective voltage decreases. For example, (a) to (C) in FIG.
The applied voltage waveform of the display cell during one frame period is shown, (a
) indicates a case where the number of display cells that are alternately lit and non-lit on the same data electrode is small, (b) indicates a medium number, and (C) indicates a large number. This inverts the polarity of the applied voltage.

In the case of a display pattern that alternately repeats lighting and non-lighting in this way, crosstalk increases, the effective voltage applied to the display cell decreases, and the transmittance decreases as a result, so (a) Compared to the display cell with the applied voltage waveform, the display cell with the applied voltage waveform (C), which has a large crosstalk, becomes darker. Therefore, display unevenness occurs and display quality deteriorates.

The present invention aims to reduce crosstalk and improve display quality.

[Means to solve the problem]

The gradation display control method of the present invention configures one pixel of a matrix display panel with a plurality of display cells, and performs gradation control by combining pixel area modulation control and frame modulation control. This will be explained with reference to the figures.

One pixel 2 in a matrix type display panel 1 in which a display cell 3 is formed at the intersection of a data electrode 4 and a scanning electrode 5 is formed by a plurality of display cells 3. In the gradation display control method that performs gradation display, pixel area modulation control is performed to select and turn on display cells within one pixel 2 according to gradation display data, and multiple display cells within one pixel 2 are controlled. The position of one display cell where frame modulation control is performed to turn only one display cell of the cells 3 into a lit or non-lighted state on a frame-by-frame basis, and frame modulation control within the pixel 2 in the direction along the data electrode 4 is performed. It is controlled by changing sequentially. Further, a data voltage is applied from the data driver 6 to the data electrode 4, and a scan voltage is applied from the scan driver 7 to the scan electrode 5.

[Effect]

The display cells 3 that form one pixel 2 between multiple frames perform gradation display by pixel area modulation control that selects and turns on the display cells 3 that form one pixel 2.
The number of gradations is increased by performing frame modulation control on one of the display cells, and the position of the display cell subject to frame modulation control is sequentially changed in the direction along the data electrode 4. For example, When one pixel 2 is composed of three display cells 3, the pixel 2 in the direction along the data electrode 4
-1 to 2-7, when pixels 2-1 to 2-6 are set to gradation level 3, 21 frames (i-〇, 1.2, 3.
), pixel 2-1 has only the rightmost display cell lit (white), pixel 2-2 has only the center display cell not lit (black), and pixel 2-3 has only the center display cell lit (black). For pixels 2-4, only the rightmost display cell is lit, for pixels 2-5, only the leftmost display cell is lit, and for pixel 2-6, only the leftmost display cell is not lit. , the next (2
In frame i+1), pixel 2-1 switches the central display cell from the non-lit state to the lit state, and pixel 2-2
pixel 2-3 switches the rightmost display cell from a lit state to a non-lit state, pixel 2-3 switches the leftmost display cell from a non-lit state to a lit state, and pixel 2-4 switches the leftmost display cell from a lit state to a non-lit state. The pixel 2-5 switches the rightmost display cell from the non-lighting state to the lighting state, and the pixel 2-6 switches the center display cell from the lighting state to the non-lighting state.

As a result, the number of data inversions in the direction along the data electrode 4 is averaged and can be made relatively small, making it possible to prevent flicker and reduce crosstalk.

[Examples] Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a processor (CPU), 12 is a display control circuit, 13 is a gradation data memory, 14 is a data switching circuit, 15 is a data distribution circuit, and 16 is a timing circuit. The signal generating circuit 17 is a matrix type display module. This matrix type display module 17 has a modular configuration including a matrix type display panel, a data driver, a scan driver, etc., and one pixel is composed of three display cells, and the gradation level is O to 6. A case in which gradation display control is performed will be described below.

Display data from an image memory or a transmission path is input to the processor 11, and 3-bit data indicating the gradation level, a frame signal, a line signal, and a data blocker signal are outputted to the display control circuit 12. 3-bit data and a frame signal are added, and the data switching circuit 1
A line signal is applied to the timing signal generating circuit 16, and a frame signal, a line signal, and a data clock signal are applied to the timing signal generating circuit 16. This timing signal generation circuit 16
Various timing signals are applied to the matrix type display module 17 from the above.

The display control circuit 12 receives a signal obtained by frequency-dividing the frame signal, and
A 4-bit signal that is a combination of the input 3-bit signal is added to the gradation data memory 13 as an address signal, and the 3-bit gradation data is read out from the gradation data memory 13 and data is replaced. added to circuit 14.

The gradation data memory 13 has, for example, the contents shown in FIG. The lower 1 bit D uses a signal obtained by dividing the frequency of the frame signal.

For example, in the case of gradation level 1, 3 of the processors 11
Since the bit data is "OO1", the address signals A-D in the 21st frame are "ooio"',
The read gradation data a"-c is "100", and the address signal A-D in the next (2i+1) frame is "
0011'', and the read gradation data a-c is '
000”.

The 3-bit gradation data a''-c corresponds to three display cells constituting one pixel, and "1" indicates a lighting state (on);
“011 indicates a non-lit state (off), so
In the case of gradation level 1, one display cell is switched between a lit state and a non-lit state by frame modulation control. Similarly, at gradation level 3.5, one display cell is switched between a lit state and a non-lit state by frame modulation control. That is, since the gradation data b at gradation level 1.3.5 is inverted every frame, only one display cell out of the three display cells has a frame variation around I'.
He will be given a 4B.

The 3-bit gradation data a to C are exchanged in a data exchange circuit 14 according to a line signal. This data switching circuit 14 has, for example, the configuration shown in FIG. 4. In the figure, 21 is a counter, 22-24 are inverters, 25-33 are AND circuits, and 34-36 are OR circuits. The counter 21 counts line signals, and the carry signal from the carry terminal CO is inverted by the inverter 22 and added to the load terminal, so that "1101"' is loaded. Also, since the lower two bits of the count contents are output, signals of "01", "10", and "11" are output according to the line signal.

For example, when the output signal of the counter 21 is "'01"', gradation data a becomes data d3 from the AND circuit 33 via the OR circuit 36, and gradation data b becomes data d3 from the AND circuit 27.
The gradation data C is passed from the AND circuit 3o to the OR circuit 35 to become data d1, and becomes data d2.

For the next line (scanning electrode), the output signal of the counter 21 is "10'°, so the gray scale data a is transmitted from the AND circuit 26 to the OR circuit 34 as data d1, and the gray scale data b is transmitted through the AND circuit 26 and the OR circuit 34. Data d2 and gradation data C are sent from the circuit 29 via the OR circuit 35 and the gradation data C is sent from the AND circuit 32 to the OR circuit 3.
6 and becomes data d3. For the next line (scanning electrode), the output signal of the counter 2 becomes "11", so the gradation data a is transferred from the AND circuit 28 to the OR circuit 35 to data d2 and gradation data b. is AND circuit 3
1 through the OR circuit 36 to data d3 and gradation data C.
is the data d1 from the AND circuit 25 via the OR circuit 34.
becomes. And for the next line (scanning electrode),
It will return to the initial state.

The data distribution circuit 15 distributes the data from the data switching circuit 14 in 4-bit parallel, 8-bit parallel, etc., depending on the configuration of the matrix display module 17, and adds the data to the matrix display module 17. .

FIG. 5 is an explanatory diagram of gradation display. As mentioned above, one pixel is composed of three display cells. For example, the upper column is 21 frames ^ the lower column is 21+1 frames, and the lighting state in each frame is shown. (ON) is white, and a non-lighted state (OFF) is black, and gradation levels 0 to 6 are shown. for example,
At gradation level 1, the rightmost display cell, at gradation level 3, the center display cell, and at gradation level 5, the leftmost display cell,
Each frame is switched on and off for each frame, but the position of the display cell that performs frame modulation control is
Pixels in the direction along the data electrode are changed sequentially.

FIG. 6 is an explanatory diagram of gradation display when adjacent pixels are included;
P1 to P4 are pixels each composed of three display cells, and are shown for the case of gradation level 3. (A) shows the case where the data for adjacent pixels is the same, and in the 21st frame, only the rightmost display cell of each pixel P1 to P4 is lit, and the brightness at that time is the same for each pixel P1 to P4. If the brightness when all display cells of P4 are turned on is 12/12, then it becomes 4/12.

In the (2i+1) frame, only the rightmost display cell is lit, and the brightness is 8/12.

In addition, (B) is a case where data for adjacent pixels are exchanged, and in the 21st frame, only the rightmost display cells of pixels P1 and P4 are in a lit state, and only the leftmost display cells of pixels P2 and P3 are in a non-lit state, In the (2i+1) frame, only the leftmost display cells of pixels Pi and P4 are in a non-lighted state, and pixels P2... Only the right end of P3 is lit, and the brightness is 6/12 in any frame. That is, (B
) has less change in brightness than the control method (A), so flicker can be prevented even at low gradation levels.

FIG. 7 is an explanatory diagram of an embodiment of low-frequency crosstalk, in which three display cells of each pixel are designated as (a) to (C) for seven pixels in the direction along the data electrode, and the 1st to 6th pixels The case where the gradation level is 3.7th pixel is set to gradation level 6 is shown. (1) is 1,3 in 21 frames.
．． For the 5th pixel, only the rightmost display cell (C) is lit,
The 2nd, 4th and 6th pixels show a case where only the leftmost display cell (a) is in a non-lit state, and the 7th pixel shows a case where all display cells are in a lit state.

Therefore, the display cells (a) and (C) of the 7th pixel are
Since the data for the 6th pixel display cells (a) and (C) indicate the non-lighting state or the lighting state, the data will not change, and the 7th pixel display cells (a) and (C) will not change.
) can be regarded as zero.

In addition, in the display cell (b) at the center of the 7th pixel, the data for the display cells (b) of the 1st to 6th pixels sequentially change between a non-lighting state and a lighting state, and the data is inverted five times. , the voltage waveform applied to the seventh pixel display cell (b) is:
It changes depending on the number of times the data is inverted.

That is, crosstalk will occur and the effective voltage will drop, causing the display cell (a).

The brightness will be lower than in (C).

Further, (2) shows the case where the data for the 1st and 3.5th pixels and the 2nd and 4.6th pixels in the 21st frame are inverted, and each display cell (a), (b), (C ), the number of data inversions is the same 5. Therefore, the voltage waveforms applied to the seventh pixel display cells (a), (b), (C) change as shown in the figure, and the seventh pixel display cells (a), (b), ( The brightness of C) will decrease.

In addition, in (3), in the 21st frame, one display cell is turned on for the 1st and 3.5th pixels, but the 1st pixel is the display cell (a), and the 3rd pixel is the display cell (b). , the 5th pixel sets the display cells (C) to the lit state, and the 2nd and 4th pixels set the two display cells to the lit state, but the 2nd pixel sets the display cells (a), (C), The fourth pixel is the display cell (a),
O)), the sixth pixel turns on display cells (b) and (C), respectively. Therefore, the number of data inversions is 4 for display cell (a), 3 for display cell (b), 2 for display cell (C), and ), [Yes]), The voltage waveform applied to (C) is
Each changes as shown in the figure, but since the number of changes is small, crosstalk is reduced, and the 7th pixel display cell (a)
.

The decrease in brightness in (b) and (C) is slight.

That is, by exchanging the gradation data a, b, and c according to the line signal using the data exchanging circuit shown in FIG.
Since the state shown in (3) in FIG. 7 can be controlled, crosstalk can be reduced.

Although the above embodiment shows a case in which one pixel is configured with three display cells, it is also possible to configure one pixel with a larger number of display cells, and frame modulation control can be performed between two frames. Although this is a case in which the process is performed, it is also possible to perform the process between even more frames. In addition, it is possible to exchange data for display cells in pixels arranged in the direction along the data electrodes using a configuration other than the configuration of the data exchange circuit shown in FIG.
It is also possible to use a replacement pattern other than the pattern shown in 3).

〔Effect of the invention〕

As explained above, the present invention provides a matrix type panel 1
One pixel 2 is constituted by a plurality of display cells 3, gradation display is controlled by pixel area modulation control and frame modulation control, and frame modulation control is performed for pixels 2 arranged in the direction along the data electrode 4. The position of each display cell 3 is sequentially changed, thereby preventing flicker and reducing the number of inversions of the data voltage applied to the data electrode 4, reducing crosstalk and improving display quality. There are advantages to being able to do so.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of a gradation data memory, FIG. 4 is a block diagram of main parts of a data switching circuit, and FIG. FIG. 5 is an explanatory diagram of gradation display, FIG. 6 is an explanatory diagram of gradation display including adjacent pixels,
FIG. 7 is an explanatory diagram of an embodiment of crosstalk reduction, and FIG. 8 is an explanatory diagram of wolfberry talk. 1 is a matrix type display panel, 2 is a pixel, 3 is a display cell, 4 is a data electrode, 5 is a scan electrode, 6 is a data driver, and 7 is a scan driver.

Claims (1)

[Scope of Claims] One pixel (2) of a matrix type display panel (1) in which a display cell (3) is formed at the intersection of a data electrode (4) and a scanning electrode (5) is connected to a plurality of said display cells ( 3),
In a gradation display control method that performs gradation display by controlling the selection of the plurality of display cells (3), a pixel that selects a display cell within the one pixel (2) and lights it up according to gradation display data. Area modulation control is performed, and one of the plurality of display cells (3) within the one pixel (2)
1 display in which frame modulation control is performed to turn only display cells into a lit or non-lit state on a frame-by-frame basis, and the frame modulation control is performed within pixels (2) arranged in a direction along the data electrode (4); A gradation display control method characterized by sequentially changing and controlling the positions of cells.