JPH05341735A - Driving circuit for liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide a driving circuit for a liquid crystal display device which can generate multi-gradation output with fewer kinds of power supply voltage and can realize it with less chip area. CONSTITUTION:This circuit is constituted of M pieces of decoding means D1-DM in which bits of input data are divided into M in accordance with line numbers M which are driven simultaneously during one horizontal scanning period and M partition input data are decoded respectively, a power source which supplies plural kinds of voltage V1-VN corresponding to numbers of output signals of M pieces of decoding means D1-DM, M pieces of selecting means S1-SM which select plural kinds of voltage V1-VM based on control of output signals of M pieces of decoding means D1-DM, and a switching means SEL which switches output of the M pieces of selecting means S1-SM by control of a control signal LN which divides one horizontal scanning period into M, and supplies successively them to signal electrode of simultaneous driving lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a liquid crystal display device, and more particularly, to display multi-gradation output by using a smaller number of power supply voltages even when displaying an interlaced video signal on a liquid crystal display panel. The present invention relates to a drive circuit of a liquid crystal display device that can be realized with a smaller chip area.

[0002]

2. Description of the Related Art A liquid crystal display device used as a video display device is rapidly improved in display quality.
It has reached the point of replacing the T (Cathod Ray Tube). Among flat display panels, active matrix type LCD (Liquid Cristal Display) is the mainstream of liquid crystal display devices, which are characterized by their thinness, light weight, and low power consumption. This has a structure in which liquid crystal is sealed between a substrate in which electrodes run in a matrix and active elements (TFTs, etc.) are connected at the intersections thereof, and a substrate in which electrodes are evenly stretched.
It's a CD. Here, the former substrate is referred to as a TFT substrate and the latter substrate is referred to as a common substrate.

FIG. 5 shows a basic configuration of a TFT substrate. As shown in the figure, data bus lines (signal electrodes) and gate bus lines (scanning electrodes) intersect in a matrix on the TFT substrate, and the TFTs 3 are connected as switching elements at all the intersections. By turning on the TFT3 of the row selected by the gate bus line,
The video signal voltage applied to the data bus line is written in each pixel electrode, and the electric charge is held until the row is selected next, whereby information is held. Since the tilt of the liquid crystal is determined according to the held information, it is possible to control the amount of light transmission and perform gradation display. Further, in the case of performing color display, it is realized by mixing lights using RGB color filters.

Since the NTCS signal of a full-color image is interlaced, it is necessary to devise it when driving it with a liquid crystal display. If the LCD is driven in the interlaced state, the brightness will drop to half. Therefore, normally, the same data is written every two horizontal lines, and the same drive is performed by shifting only one horizontal line for each field. This prevents the brightness from decreasing and the resolution is 70%.
% Can be maintained.

FIG. 6 shows a block diagram of a conventional LCD driver. As shown in the figure, the LCD driver of this conventional example includes a shift register 11, a data register 12, a data latch 13, and a decoder and selector 21.

The shift register 11 receives the input data R,
The timing for writing G and B into the data register 12 is controlled. Under the control of the shift register 11, when the input data R, G, and B are written into the data register 12 for one line, It is passed to the data latch 13. Further, depending on the combination of the values held in the data latch 13, the power supply voltage VP0 is passed through the selector 21.
1 to VP16 (power supply voltage for positive polarity) and VM01 to VM
16 (power supply voltage for negative polarity) is selected.

In other words, the power supply voltage for gradations is required, but in practice, AC drive is generally used to prevent deterioration of the liquid crystal, and the number of power supplies is twice the number of gradations. A voltage is needed. For example, to output 16 gradations, 32 kinds of power supply voltages are required. The power supply voltage and the selector portion occupy about half of the chip area, which greatly hinders miniaturization.

[0008]

As described above,
The drive circuit of the conventional liquid crystal display device requires a power supply voltage for gray scales, and particularly when AC driving is performed, a power supply voltage of twice the number of gray scales is required. Since it occupies about half of the chip area, there is a problem that it hinders the miniaturization of the drive circuit.

The present invention solves the above problems.
It is an object of the present invention to provide a drive circuit of a liquid crystal display device which enables multi-gradation output with a smaller number of power supply voltages and can be realized with a smaller chip area.

[0010]

In order to solve the above-mentioned problems, the drive circuit of the liquid crystal display device of the first feature of the present invention is
As shown in FIG. 1, the bit of the input data is divided into M according to the number M of lines (M is an arbitrary positive integer, M = 2 in FIG. 1) that are simultaneously driven in one horizontal scanning period, and the M division is performed. M decoding means D1 for respectively decoding the input data
To DM, a power supply for supplying a plurality of types of voltages V1 to VN corresponding to the number of output signals of the M decoding means D1 to DM, and control of output signals of the M decoding means D1 to DM, It is configured to have M selection means S1 to SM for selecting the plurality of types of voltages V1 to VN.

According to a second aspect of the present invention, there is provided a drive circuit for a liquid crystal display device, wherein the drive circuit for the liquid crystal display device according to claim 1 controls the control signal LN for dividing one horizontal scanning period by M. The switching means SEL is configured to switch the outputs of the individual selecting means S1 to SM and sequentially supply the signal electrodes to the simultaneously driven lines.

A drive circuit for a liquid crystal display device according to a third aspect of the present invention is the drive circuit for a liquid crystal display device according to claim 1 or 2, wherein the M selection means S1 to SM are supplied. The voltages have different polarities.

Further, in the drive circuit of the liquid crystal display device according to the fourth feature of the present invention, in the drive circuit of the liquid crystal display device according to claim 1, 2, or 3, the input data is an interlace system image. It is a signal.

[0014]

In the drive circuit of the liquid crystal display device having the first, second and fourth characteristics of the present invention, as shown in FIG. 1, the number M of lines simultaneously driven within one horizontal scanning period (M is an arbitrary positive number). It is an integer, and (4 bits) input data is divided into M according to (M = 2) in FIG. 1, and the M divided (2 bits) input data is decoded by M decoding means D1 to DM, respectively. (4) control signals (C1-C4 and C5-C)
8), and the M number of selection units S1 to SM output the control signals (C1 to C4 and C5 to C) from the decoding units D1 to DM to the plurality of types of voltages V1 to VN supplied from the power source.
8) Select and output. For example, the selecting means S1 selects one of the voltages V1 to V4 by the control signal (C1 to C4) from the decoding means D1. Further, in the switching means SEL, the outputs of the M selection means S1 to SM are switched by the control of the control signal LN that divides one horizontal scanning period into M, and the signals are sequentially supplied to the simultaneous drive lines and driven. I am trying.

Therefore, M types of power supply voltages are sequentially selected and displayed on the line for simultaneous driving.
If considered as a set, it will be possible to visually average and to represent multiple gradations with fewer types of power supply voltages. For example,
In the example of FIG. 1 (M = 2, 4-bit input data), 4 × 4 = 16 gradations can be expressed with eight types of power supply voltages. In particular, when displaying an interlaced video signal on a liquid crystal display panel, multi-gradation output is possible with a small power supply voltage.

Further, in the drive circuit of the liquid crystal display device of the third feature of the present invention, the voltages supplied to the M selection means S1 to SM have polarities different from each other, so that the cycle is shorter. AC drive is possible, and an image with little flicker can be realized.

[0017]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 2 shows a configuration diagram of a drive circuit of a liquid crystal display device according to an embodiment of the present invention. The drive circuit of the liquid crystal display device of this embodiment is effective in the case where the same data is written in two lines in order to display an interlaced video signal on the liquid crystal display panel. In this example,
Consider a case where 4-bit input data of each color of RGB is considered as a video signal and output display of 16 gradations is performed.

In FIG. 2, the drive circuit of the liquid crystal display device of the present embodiment comprises a shift register 11 and a data register 1.
2, data latch 13, and decoder and selector 1
It is composed of 4. Further, SP is a start pulse from a control circuit (not shown), and R, G, and B are 4 respectively.
Bit input data, CLK is an operation clock which is given in synchronization with the input data or is generated by a control circuit,
LP is a latch pulse, V1P to V8P are positive power supply voltages, and V1M to V8M are negative power supply voltages.

The shift register 11 has input data R,
The timing for writing G and B in the data register 12 is controlled, and the start pulse S is set for each line.
Given P, it generates a timing signal. Under the control of the shift register 11, when the input data R, G, and B are written in the data register 12 for one line,
It is passed to the data latch 13 in the next stage. Further, depending on the combination of the values held in the data latch 13, the power supply voltages V1P to V8P and V are passed through the decoder and selector 14.
1M to V8M are selected.

FIG. 1 shows a detailed circuit diagram of the decoder and selector 14. The circuit shown in the figure is a partial circuit for the input data R. In the figure, LN which divides one horizontal scanning period into two is a line inversion signal. A timing chart for explaining the operation of this embodiment is shown in FIG.

In FIG. 1, the decoder and selector 14
Are two decoding means D1 and D2 for respectively decoding the divided input data, and decoding means D1 and D
2 types of output signals corresponding to 4 types of power supply voltage V
1 to V4 and V5 to V8 are converted to decoding means D1 and D2
The output of the selecting means S1 and S2 is switched by the control of the line inversion signal LN and the two selecting means S1 and S2 which are respectively selected based on the control of the output signal of the above, and the signal electrodes are sequentially supplied to the two lines of simultaneous driving. Switching means S
It is composed of EL. In addition, a plurality of types of power supply voltage V1
To V4 and V5 to V8, the positive polarity power supply voltage V1P to
V8P or a negative polarity power supply voltage V1M to V8M is supplied.

In the decoder and selector 14, for the first line of the two lines in which the same data is written, the power supply voltage V corresponding to the lower 2 bits of the input data R.
The voltage selected from 5 to V8 is written, and the voltage selected from the power supply voltages V1 to V4 corresponding to the upper bit of the input data R is written to the next second line.

The operation of this embodiment will be described with reference to FIG. 2 during one cycle of the NTSC horizontal sync signal Hsync
When writing is attempted to the liquid crystal cells for lines, the period of the line inversion signal LN becomes half of the horizontal synchronization signal Hsync.

The start pulse SP becomes effective at the beginning of the video signal, and the transfer to the data register 12 is sequentially performed. Then, by the latch pulse LP, the data register 1
The transfer from 2 to the data latch 13 is performed, and the voltage corresponding to the data of one line is selected. Two kinds of power supply voltages are selected in order, but if one set of two lines is considered, they can be visually averaged, and it is possible to express multiple gradations with less kinds of power supply voltages.

FIG. 4A shows an example of setting the power supply voltages V1 to V8. The figure (2) is an average voltage of two types of power supply voltages, and the figure (3) is a diagram for explaining the correspondence between the output average voltage and the gradation. As described above, in this embodiment, 4 × 4 = 16 gradations can be expressed with eight kinds of power supply voltages. Compared with the conventional example, a power supply voltage of 1/2 is required, which can greatly contribute to high integration.

Further, in the present embodiment, in order to prevent deterioration of the liquid crystal, AC driving is performed in units of horizontal scanning period.
If the power supply voltage having different polarities is selected for each line in the horizontal scanning period, the polarity inversion drive can be performed, and an image with less flicker can be realized.

[0027]

As described above, according to the present invention,
The input data is divided into M according to the number M of lines to be driven simultaneously in one horizontal scanning period (M is an arbitrary positive integer), and the M divided input data are decoded by M decoding means to generate control signals. The M selection units generate a plurality of types of voltages supplied from the power source by the control signal from the decoding unit and output the selected voltages.
The output of the M selection means is switched by the control of the control signal for dividing one horizontal scanning period into M, and the signal electrodes are sequentially supplied to the simultaneously driven lines to be driven. The power supply voltages of different types are selected and displayed in order, but if one set of M lines is considered, they are visually averaged, and it is possible to express multiple gradations with fewer types of power supply voltages. It is effective when displaying the video signal of the system on the liquid crystal display panel, and as a result, it is possible to provide the drive circuit of the liquid crystal display device which can be realized with a smaller chip area.

Further, according to the present invention, since the voltages supplied to the M selection means are different in polarity from each other, AC driving can be performed in a shorter cycle, and an image with less flicker can be realized. It is possible to provide a driving circuit for a different liquid crystal display device.

[Brief description of drawings]

FIG. 1 is a detailed circuit diagram of a decoder and a selector of a drive circuit of a liquid crystal display device of the present invention.

FIG. 2 is a configuration diagram of a drive circuit of a liquid crystal display device according to an embodiment of the present invention.

FIG. 3 is a timing chart explaining the operation of the drive circuit of the liquid crystal display device of the example.

FIG. 4 (1) is an explanatory diagram of set values of power source voltages V1 to V8, FIG. 4 (2) is an explanatory diagram of an average voltage of two types of power source voltages, and FIG. 4 (3) is an output average voltage. It is explanatory drawing of the correspondence of a gradation.

FIG. 5 is a basic configuration diagram of a TFT substrate.

FIG. 6 is a configuration diagram of a drive circuit of a conventional liquid crystal display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal panel 3 ... TFT D1-DM ... Decoding means V1-VN ... Power supply voltage S1-SM ... Selection means SEL ... Switching means LN ... Control signal (line inversion signal) 11 ... Shift register 12 ... Data register 13 ... Data latch 14, 21 ... Decoder and selector Hsync ... Horizontal synchronization signal SP ... Start pulse R, G, B ... Input data (4 bits) CLK ... Operation clock LP ... Latch pulse V1P to V8P, VP01 to VP16 ... Power supply voltage for positive polarity V1M -V8M, VM01-VM16 ... Power supply voltage for negative polarity

Claims (4)

[Claims] 1. A bit of input data is divided into M according to the number of lines M (M is an arbitrary positive integer) that are simultaneously driven in one horizontal scanning period, and M pieces of the input data divided into M are decoded respectively. Decoding means (D1 to DM), a power supply for supplying a plurality of types of voltages (V1 to VN) corresponding to the number of output signals of the M decoding means (D1 to DM), and the M decoding means ( A drive circuit for a liquid crystal display device, comprising M selection means (S1 to SM) for selecting the plurality of types of voltages (V1 to VN) based on control of output signals of D1 to DM). 2. The drive circuit of the liquid crystal display device is controlled by a control signal (LN) for dividing one horizontal scanning period into M,
2. The liquid crystal display device according to claim 1, further comprising switching means (SEL) for switching the outputs of the M selection means (S1 to SM) and sequentially supplying the signal electrodes to the simultaneously driven lines. Drive circuit. 3. The driving circuit of the liquid crystal display device according to claim 1, wherein the voltages supplied to the M selection units (S1 to SM) have polarities different from each other. 4. The drive circuit for a liquid crystal display device according to claim 1, wherein the input data is an interlaced video signal.