JP3346516B2 - Video processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video processing circuit,
More specifically, the present invention relates to a process of providing a black or gray frame around a display image on a PDP (plasma display panel) or an LCD (liquid crystal display).

[0002]

2. Description of the Related Art In the case of displaying an image on a PDP or LCD, the display ratio is high. Therefore, there is a case where it is necessary to provide a black frame around the screen (left, right, up and down) because it is necessary to slightly remove the surrounding video components. In the case where the display element is a conventional cathode ray tube, it is easy to realize the provision of the black frame by changing the phase or width of the horizontal or vertical blanking signal. However, in the PDP or LCD, due to the nature of digital display, when the horizontal display control signal or the vertical display control signal as a display control signal becomes high (H), respectively, the left end of the screen (horizontal) or the top of the screen. It has the property that the display range is determined starting from (vertical). Therefore,
Even if the width of the blanking signal is simply changed, a black frame cannot be easily provided like a CRT.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned background, and has been developed in PDP or LCD.
It is an object of the present invention to provide a video processing circuit which uses a horizontal display control signal and a vertical display control signal for defining the display range and provides a black frame or a band around a screen.

[0004]

SUMMARY OF THE INVENTION According to the present invention, there is provided a video signal processing system comprising three primary color digital signals of a red video signal, a blue video signal and a green video signal each having a predetermined number of bits. A counter that starts counting a predetermined clock signal from a start point of a horizontal display control signal used for setting a video display range in the direction, and clears a count at an end point of the control signal; A first decoder that outputs a first decode pulse having a predetermined width when the count value reaches 1, and a second decoder that counts by the counter reaches a predetermined second count value larger than the first count value. A second decoder that outputs a second decode pulse; and a second decoder that is set by the first decode pulse and outputs the second decode pulse. A flip-flop that is reset by a decode pulse and outputs a pulse signal of a predetermined width based on the same set and reset, a pulse signal from the flip-flop, and any one video signal determined from the three primary color signals An arithmetic circuit that performs a logical product operation and outputs a video signal only during the same pulse signal is provided, and a video signal from the arithmetic circuit and a video signal other than the determined one video signal are displayed. Another object of the present invention is to provide a video processing circuit which does not perform video display for the identified one video signal during a predetermined period at the left end and the right end of the screen.

[0005]

The basic feature of the present invention is to set the video data in the area where the black band or frame is provided to "zero". The first counter, the first decoder, the second decoder, and the first flip-flop use the horizontal display control signal, and use a required range of the left and right ends in the horizontal direction and a required pulse (zero) for setting the video component to zero. (First pulse) signal. The logical product of the first pulse and the video signal is obtained (AND gate). As a result, there is no video component in the required range at the left and right ends in the horizontal direction, and a black band is formed.

The same operation as described above is performed in the vertical direction. That is, the second counter, the third decoder, the fourth decoder, and the second flip-flop use the vertical display control signal, and have a required range of the upper and lower ends in the vertical direction, and a required range for setting the video component to zero. A pulse (second pulse) signal is generated. The logical product of the second pulse and the video signal is obtained (AND gate). As a result, there is no video component in the required range at the upper and lower ends in the vertical direction, and a black band is formed. Then, the first pulse and the second pulse are combined (synthesizing unit), and a logical product of the combined pulse and the video component is obtained to form a black frame. Further, if the logical product is processed so as to be performed only for each predetermined bit in each of the red, blue and green video digital data, the video component does not become completely zero, and the band or frame can be made gray. Further, for a predetermined color among red, blue and green, a logical band is obtained by taking a logical product of the predetermined bits.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image processing circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a main part block diagram showing an embodiment of a video processing circuit according to the present invention, FIG. 2 is a main part block diagram showing another embodiment, and FIG. 3 is a time chart and a screen form for explaining the present invention. FIG. 4 is a time chart showing a video signal (a) and a horizontal or vertical display control signal (b) for understanding the present invention.

In FIG. 1, reference numeral 1 denotes a horizontal display control signal.
The first counter which starts counting the predetermined clock signal CK1 at the start timing of Sh and is cleared at the end timing is a timing at which the first counter 1 sets the video component to zero in a predetermined range at the left end of the screen. , A first decoder that outputs a first decode pulse P1 having a predetermined width when the first count value has reached the first count value, and a timing at which the first counter 1 sets the video component to zero in a predetermined range at the right end of the screen. The second decoder 4 outputs a second decode pulse P2 having a predetermined width when the count value reaches a second count value that determines the second count value. The second decode pulse P2 is set by the first decode pulse P1 and reset by the second decode pulse P2. This is a first flip-flop (hereinafter, referred to as a first FF) that outputs a first pulse signal Ph having a required width.

Reference numeral 5 denotes a second counter which starts counting the predetermined clock signal CK2 at the start timing of the vertical display control signal Sv, and the count is cleared at the end timing. A third decode pulse having a predetermined width when the count reaches a third count value that determines the timing at which the video component is reduced to zero for a predetermined range at the upper end;
A third decoder that outputs P3, 7 is a second counter 5
But a fourth decoder that outputs a fourth decoder pulse P4 having a predetermined width when it reaches the fourth count value defining the timing of the zero video component per predetermined range of a screen bottom, the said third decoding 8 A second flip-flop (hereinafter, referred to as a second FF), which is set by a pulse P3, is reset by the fourth decode pulse P4, and outputs a second pulse signal Pv of a required width, and 9 is the first flip-flop. Of the pulse signal Ph and the second pulse signal Pv.
A synthesizing unit 10 that outputs P5 is an AND gate that performs a logical product operation of the synthesized pulse signal P5 and the video data Di.

In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and 21 is a composite pulse signal P5 from the synthesizing unit 9.
An inverter 22 for performing a logical sum operation of the pulse signal from the inverter 21 and a predetermined bit of the video data Di; and 23, each bit of the video data excluding the predetermined bit and the composite pulse signal P5. AND gate which performs a logical AND operation of.

The basic principle of the present invention is to make a black or gray band by lowering or lowering the video component level in a required range at the left and right ends or upper and lower ends of the screen. That is, if this is performed at the left and right edges of the screen, the left and right edges will be strip-shaped, if performed at the upper and lower edges, the upper and lower edges will be strip-shaped, and if both are performed, a frame will be formed.
If the image components in the required range are all zero in the three primary colors, the band and the like become black. If all the three primary color signals are lowered at the same level, the band becomes gray. Etc. are colored. Hereinafter, the operation of the present invention will be described for each of the above basics.

[1] Generation of Black Band Shape and Black Frame (FIG. 1) FIG. 1 shows a configuration for generating a black frame. This black frame is obtained by synthesizing the left and right bands and the upper and lower bands. The first counter 1 to the first FF 4 correspond to the generation of left and right bands, and the second counter 5 to the second FF 8 correspond to the generation of upper and lower bands. FIG. 1 illustrates one color signal of the three primary color signals when the video signal Di is composed of three primary color signals of red (R), blue (B), and green (G). Therefore, in the configuration shown in FIG.
The gate 10 is provided for each color signal. here,
The horizontal display control signal Sh and the vertical display control signal Sv input to each counter will be described. PDP and LCD
Requires a control signal to display a screen in a predetermined range. This signal consists of horizontal and vertical signals,
In the present invention, the former is called a horizontal display control signal Sh, and the latter is called a vertical display control signal Sv.

FIG. 4 shows the phase relationship between the horizontal or vertical display control signal (b) and the video signal (a). T11 in the video signal shown in the figure represents one horizontal or vertical cycle. Ts in the horizontal or vertical display control signal is a display start timing, and Tf is a display end timing. That is, the display is made high (H) and non-display is made low (L). The display start timing Ts is at the left end of the horizontal display control signal Sh with respect to the screen, and at the same or upper end with respect to the vertical display control signal Sv (each means a scanning start point). Since both of these display control signals Sh and Sv are used, the start point of the screen display is the left end and the upper end of the screen (that is, the upper left corner). After the display of the period T12 with the same Ts as the display start point, the display ends at Tf.
This display is repeated in one horizontal cycle or one vertical cycle. Each display control signal has such a property and is generated in the apparatus as an existing signal. In the present invention, the horizontal display control signal Sh and the vertical display control signal Sv
Use

(1) Generation of Black Bands at Left and Right Edges of the Screen As shown in FIG. 3, the first counter 1 receives a predetermined clock signal CK at the start timing T1 of the horizontal display control signal Sh.
The count of 1 is started, and the count is cleared at the end timing T2 ((b) and (c)). FIG. 3A shows a video signal Di, and T means a horizontal cycle here. In the counting by the first counter 1, when the count reaches a predetermined count value (first count value) after the count is started (T3), the first decoder 2 outputs a pulse of a predetermined width (first decode pulse P1). Is output (D). Further, when the count value reaches the second count value (T4), the second decoder 3 outputs a second decode pulse P2 having a predetermined width (see FIG. 8). The first FF 4 is set by the first decode pulse P1 (T3) and is reset by the second decode pulse P2 (T3
Four). As a result, the first pulse signal Ph having the width T5 is output from the first FF 4 (figure F).

When the black band is provided only on the left and right edges of the screen, the synthesizing unit 9 is unnecessary, and the first pulse signal Ph from the first FF 4 and the video data Di (shown in FIG. Perform logical AND operation. Since the video data Dv has a predetermined number of bits (for example, 8 bits), the above operation is performed for each bit from the most significant bit (MSB) to the least significant bit (LSB). The video data Do obtained by this operation is the target video output, and as shown in FIG. 6G, the video data in which the video components in the horizontal period T6 and T7 have become zero with respect to the original video data Di. is there. When this video data Do is displayed under the control of the horizontal direction control signal Sh, the left end T6 and the right end T7 of the screen are not displayed as a video but have a black band as shown in FIG.

(2) Generation of a black band at the upper and lower ends of the screen Basically, a black band is provided at the upper and lower ends of the screen.
3 except that the signal input to the second counter 5 is different. As the clock signal CK2, a horizontal synchronizing signal or a signal having a horizontal cycle such as the above-described horizontal display control signal Sh is used. The vertical display control signal Sv is used as a signal for starting and clearing the count. Thereafter, the second counter 5, the third tecoder 6, the fourth decoder 7, and the second FF 8 operate for the same purpose as in (1) above with reference to the vertical cycle. That is, if FIG. 3 is also used, the second counter 5 starts counting the predetermined clock signal CK2 at the start timing T1 of the vertical direction display control signal Sv and clears the count at the end timing T2 (B, C). Figure). FIG. 3A shows a video signal, and T means a vertical cycle here.

In the counting by the second counter 1, when a predetermined count value (third count value) is reached (T3) after the start of counting, the third decoder 6 outputs a pulse of a predetermined width (third decode value). Pulse P3) is output (D). Further, when the count value reaches the fourth count value (T4), the fourth decoder 7 outputs a fourth decode pulse P4 having a predetermined width (see FIG. 8). The second FF8 is the third FF8.
(T3), and is reset by the fourth decode pulse P4 (T4). Thereby, the second
FF8 outputs a second pulse signal Pv having a width T5 (figure). When the black band is provided only at the upper and lower ends of the screen, the synthesizing unit 9 is unnecessary as in the previous section, and the second pulse signal Pv from the second FF 8 and the video data Di (FIG.
An AND operation is performed by the ND gate 10. Since the video data Di has a predetermined number of bits (for example, 8 bits), the above operation is performed for each bit from the most significant bit (MSB) to the least significant bit (LSB). The video data Do obtained by this operation is the target video output, and as shown in FIG. 8G, the video data in which the video components in the vertical T6 and T7 periods are zero with respect to the original video data Di. is there. When this video data Do is displayed under the control of the vertical direction control signal Sv, the upper end T8 and the lower end T9 of the screen are not displayed as a video but have a black band shape as shown in FIG.

(3) Generation of a black frame around the screen (left and right ends and upper and lower ends) By performing both of the above items (1) and (2), the periphery of the screen becomes a black frame. FIG. 1 itself is a configuration for generating the black frame. In the figure, the first pulse signal from the first FF 4 is output by the synthesizing unit 9.
Ph and the second pulse signal Pv from the second FF 8 are synthesized. An AND operation is performed between the synthesized pulse signal P5 and each bit of the video data Di. The video data Do obtained by this calculation is the target video output. When this video data Do is displayed under the control of the horizontal direction control signal Sh and the vertical direction control signal Sv, the left end T6, right end T7,
The upper end T8 and the lower end T9 are not displayed as images but are black frames.

[2] Generation of gray band and frame (FIG. 2) [1] In (1) to (3) of [1], the level of the video component in the band or frame around the screen is set to zero, and the band or frame is formed. The frame was black. As this application, there is a method of lowering the level of a video component instead of reducing it to zero. If all three primary color signals are reduced at the same ratio, a band or frame of an intermediate gradation between white and black (that is, gray) can be generated. FIG. 2 is a configuration diagram for generating this gray band or frame. Reference numerals 1 to 9 are the same as those in FIG. As a method of lowering the video level, a method of setting bits other than the most significant bit (MSB) of the video data Di to zero will be described as an example. The frame in this case is 50% gray (level decrease rate
50%).

An inverter 21 is provided at a stage subsequent to the synthesizing unit 9 and a synthesized pulse signal P5 output from the synthesizing unit 9 is output to the inverter 21.
21 and A provided for each bit other than the MSB
The signal is branched to the ND gate 23 and sent. An OR gate 22 for performing a logical sum operation is provided at a subsequent stage of the inverter 21. The combined pulse signal P5 is inverted by the inverter 21, and the logical sum of the inverted combined pulse signal P6 and the MSB of the video data Di is calculated by the OR gate 22. As a result, the data relating to the MSB is output as "1" instead of being zero.

On the other hand, video data other than the MSB is AND
By performing a logical product operation in the gate 23 as in the case of FIG. As a result, the output data Do passes the MSB component (becomes "1"), and the data relating to the other bits other than the MSB becomes zero, resulting in video data reduced by 50% level. By performing the above processing for each of the three primary color signals, the gradation of the band or frame becomes 50% gray. If the above processing is performed only on the left and right ends, a predetermined width at the left and right ends becomes a 50% gray band, and if the processing is performed only on the upper and lower ends, a predetermined width at the upper and lower ends becomes a 50% gray band. In addition, if both left and right and up and down are performed, the periphery becomes a 50% gray frame.

[3] Generation of colored bands and frames (FIGS. 1 and 2) The above item [1] is a method for setting the video level in the range of the bands or frames to zero. These methods lower the video level in the same range, but perform the same processing for all three primary color signals of red, blue and green that make up the video signal. On the other hand, the process of reducing or lowering the video level is
By performing one color or two colors of the three primary color signals, bands or frames of various colors can be obtained. For example,
If only one color of the red signal is set to zero, a cyan color composed of the other two colors (blue and green) is obtained (provided that the blue and green components are equally present), and the two colors (blue and green) are set to zero. If it does, it will become red of one other color.

Specifically , the following combinations are conceivable. (1) The video level is set to zero for the determined one or two color signals, and no processing is performed for the other color signals. in this case,
If one color is set to zero, the other two colors are used. For example, if red is set to zero, cyan is used (provided that the other two colors are equally present). ), If green is set to zero, the color becomes magenta (same as above).
Color system.

(2) The video level is lowered for the determined one or two color signals, and no processing is performed for the other color signals.
In this case, when the level of one color is lowered, the color obtained by adding the reduced color to the color obtained when the one color is set to zero becomes a color,
For example, when the level of red is reduced, cyan (but other two
If the colors are evenly distributed), the reduced level red is added to the color, and if the levels of the two colors are reduced, the remaining one color becomes the emphasized color.

(3) The video level is set to zero for the determined one color signal, and the video level is reduced for the other two color signals. In this case, a low-luminance color composed of two colors that are not zero in the above item (1) is obtained. (4) The video level is set to zero for the determined two color signals, and the video level is reduced for the other one color. In this case, the color is a low-luminance color composed of one color that is not zero in the item (1). If the above processes (1) to (4) are performed on the left and right sides of the screen, the left and right bands are obtained. In this case, the processing method for each color is the above item [1] or [2].

[0026]

As described above, according to the present invention, P
A band or a frame can be provided around a display image such as a DP or an LCD. Further, by performing the basic processing method in combination with the three primary color signals and only on the left and right sides or only on the upper and lower sides of the screen, and further on both of them, it is possible to obtain black, gray and further colored bands or frames. This is an effective means when it is desired to remove a peripheral image or as one decorative process. In a conventional CRT display, a band or a frame can be relatively easily provided around a screen by processing of a blanking signal. However, in a PDP, an LCD, or the like, a fundamental difference in a display driving method is different from that of a CRT. It was not possible to easily set a band or a frame. Therefore,
The present invention provides a new technology.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing an embodiment of a video processing circuit according to the present invention.

FIG. 2 is a main block diagram showing another embodiment of the video processing circuit according to the present invention.

FIG. 3 is a time chart for explaining FIG. 1 or FIG. 2;

FIG. 4 is a time chart for understanding the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st counter 2 1st decoder 3 2nd decoder 4 1st flip-flop 5 2nd counter 6 3rd decoder 7 4th decoder 8 2nd flip-flop 9 synthesis | combination part 10 AND gate 21 inverter 22 OR gate 23 AND gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/20 660 G09G 3/20 632 G09G 3/28 H04N 5/66 102

Claims (13)

(57) [Claims] In processing of a video signal composed of three primary color digital signals of a red video signal, a blue video signal and a green video signal each having a predetermined number of bits, a horizontal video display range on a plasma display panel is set. A counter that starts counting a predetermined clock signal from the start point of the horizontal display control signal to be provided and clears the count at the end point of the control signal; and when the count by the counter reaches a predetermined first count value. A first decoder that outputs a first decode pulse having a predetermined width, and outputs a second decode pulse when a count by the counter reaches a predetermined second count value that is larger than the first count value. A second decoder, the second decoder being set by the first decode pulse;
A flip-flop which is reset by a decode pulse of the same and outputs a pulse signal of a predetermined width based on the same set and reset, a pulse signal from the flip-flop, and any one of the three primary color signals, And an arithmetic circuit for performing a logical product operation and outputting a video signal only during the same pulse signal is provided, and a video signal from the arithmetic circuit and a video signal other than the predetermined one video signal are displayed. The video processing circuit according to claim 1, wherein the video display is not performed for the identified one video signal in a predetermined period at the left end and the right end of the screen. 2. A process for setting a vertical video display range in a plasma display panel in processing a video signal composed of three primary color digital signals of a red video signal, a blue video signal and a green video signal each having a predetermined number of bits. A counter that starts counting the horizontal synchronization signal from the start point of the vertical display control signal to be provided and clears the count at the end point of the control signal; and a counter that counts when the count by the counter reaches a predetermined first count value. A first decoder that outputs a first decode pulse having a width, and a second decoder that outputs a second decode pulse when the count by the counter reaches a predetermined second count value larger than the first count value.
And a flip-flop that is set by the first decode pulse, is reset by the second decode pulse, and outputs a pulse signal of a predetermined width based on the set and reset. An arithmetic circuit that performs an AND operation on the pulse signal from the flip-flop and any one of the three primary color signals and outputs a video signal only during the same pulse signal; By displaying the video signal from the arithmetic circuit and the video signal other than the determined one video signal, video display is performed for the identified one video signal in predetermined periods at the upper and lower edges of the screen. A video processing circuit characterized in that it is not provided. 3. In the processing of a video signal composed of three primary color digital signals of a red video signal, a blue video signal and a green video signal each having a predetermined number of bits, a horizontal video display range is set on a plasma display panel. A first counter that starts counting a predetermined clock signal from the start point of the horizontal display control signal to be provided and clears the count at the end point of the control signal; and a first counter that counts by the first counter. When the count value is reached, a first decode pulse for outputting a first decode pulse of a predetermined width is output.
A second decoder that outputs a second decode pulse when the count by the first counter reaches a predetermined second count value larger than the first count value; A first flip-flop that is set by a decode pulse and is reset by the second decode pulse and outputs a first pulse signal having a predetermined width based on the set and reset; and a vertical image display range in the plasma display panel. A second counter that starts counting the horizontal synchronizing signal from the start point of the vertical display control signal used for the setting, and clears the count at the end point of the control signal; and a second counter that counts by the second counter. A third decoder that outputs a third decode pulse of a predetermined width when the count value reaches 3. A fourth decoder that outputs a fourth decode pulse when the count by the counter reaches a predetermined fourth count value larger than the third count value; and a fourth decoder that is set by the third decode pulse. 4, a second flip-flop that outputs a second pulse signal of a predetermined width based on the same set and reset, a first pulse signal from the first flip-flop, A synthesizing unit for synthesizing the second pulse signal from the flip-flop, and calculating the logical product of the pulse signal from the synthesizing unit and any one of the three primary color signals. , An arithmetic circuit that outputs a video signal only during the period of the first pulse signal and the second pulse signal, and the video signal from the arithmetic circuit and the predetermined 1 The video signal other than the video signal is displayed, so that no video display is performed for the identified one video signal in a predetermined period of the left edge, the right edge, the upper edge, and the lower edge of the screen. Video processing circuit. 4. The arithmetic circuit is provided so as to perform the arithmetic for each of two video signals determined from the three primary color signals, and a video signal from each of the arithmetic circuits and the determined 2 By displaying the video signals other than the two video signals, the two video signals identified are not displayed during a predetermined period of the left edge, the right edge, the upper edge, and the lower edge of the screen. The video processing circuit according to claim 3. 5. In a processing of a video signal composed of three primary color digital signals of a red video signal, a blue video signal and a green video signal each having a predetermined number of bits, a horizontal video display range is set on a plasma display panel. A counter that starts counting a predetermined clock signal from the start point of the horizontal display control signal to be provided and clears the count at the end point of the control signal; and when the count by the counter reaches a predetermined first count value. A first decoder that outputs a first decode pulse having a predetermined width, and outputs a second decode pulse when a count by the counter reaches a predetermined second count value that is larger than the first count value. A second decoder, the second decoder being set by the first decode pulse;
A flip-flop that outputs a pulse signal of a predetermined width based on the same set and reset, an inverter that inverts the pulse signal from the flip-flop, a pulse signal from the inverter, and the three primary color signals A first arithmetic circuit that performs a logical sum operation on any one-bit video data in any one video signal determined from among the above, a pulse signal from the flip-flop, and any one of the predetermined one A second arithmetic circuit which performs a logical AND operation on each of the video signals of the other bits except for the arbitrary bit in the video signal and outputs the video signal only during the period of the same pulse signal; And displaying a video signal from the arithmetic circuit and a video signal other than the determined one video signal. More, the video processing circuit being characterized in that so as to lower the video level in the left and right edges of the predetermined time period of the screen for one of the video signal which defines the. 6. In a processing of a video signal composed of three primary color digital signals of a red video signal, a blue video signal and a green video signal each having a predetermined number of bits, a video display range in a vertical direction on a plasma display panel is set. A counter that starts counting the horizontal synchronization signal from the start point of the vertical display control signal to be provided and clears the count at the end point of the control signal; and a counter that counts when the count by the counter reaches a predetermined first count value. A first decoder that outputs a first decode pulse having a width, and a second decoder that outputs a second decode pulse when the count by the counter reaches a predetermined second count value larger than the first count value.
And a flip-flop that is set by the first decode pulse, is reset by the second decode pulse, and outputs a pulse signal of a predetermined width based on the set and reset. Inverter for inverting the pulse signal from the flip-flop, AND operation of a logical sum of the pulse signal from the inverter, and any one-bit video data in any one video signal determined from the three primary color signals And a pulse signal from the flip-flop and a video signal of each of the other ones of the predetermined one of the video signals excluding the arbitrary bit are subjected to AND operation. And a second arithmetic circuit provided for each bit for outputting a video signal only during the period of the pulse signal. By displaying the video signal from the arithmetic circuit and the video signal other than the determined one video signal, the identified one video signal has a video level in a predetermined period at the upper and lower ends of the screen. A video processing circuit characterized by lowering the image quality. 7. In the processing of a video signal composed of three primary color digital signals of a red video signal, a blue video signal and a green video signal each having a predetermined number of bits, a horizontal video display range is set on a plasma display panel. A first counter that starts counting a predetermined clock signal from the start point of the horizontal display control signal to be provided and clears the count at the end point of the control signal; and a first counter that counts by the first counter. When the count value is reached, a first decode pulse for outputting a first decode pulse of a predetermined width is output.
A second decoder that outputs a second decode pulse when the count by the first counter reaches a predetermined second count value larger than the first count value; A first flip-flop that is set by a decode pulse and is reset by the second decode pulse and outputs a first pulse signal having a predetermined width based on the set and reset; and a vertical image display range in the plasma display panel. A second counter that starts counting the horizontal synchronizing signal from the start point of the vertical display control signal used for the setting, and clears the count at the end point of the control signal; and a second counter that counts by the second counter. A third decoder that outputs a third decode pulse of a predetermined width when the count value reaches 3. A fourth decoder that outputs a fourth decode pulse when the count by the counter reaches a predetermined fourth count value larger than the third count value; and a fourth decoder that is set by the third decode pulse. 4, a second flip-flop that outputs a second pulse signal of a predetermined width based on the same set and reset, a first pulse signal from the first flip-flop, A combining unit that combines the second pulse signal from the flip-flop, an inverter that inverts the pulse signal from the combining unit, a pulse signal from the inverter, and one of the three primary color signals. A first arithmetic circuit for performing a logical sum operation on arbitrary 1-bit video data in the video signal, and a pulse signal from the synthesizing unit; A logical AND operation is performed on each of the video signals of the other bits except for the arbitrary bit in the determined one video signal, and a video signal is output only during the period of the same pulse signal. Two arithmetic circuits, and displaying the video signal from the arithmetic circuit and the video signal other than the determined one video signal, the left edge, the right edge, An image processing circuit, wherein an image level is lowered in predetermined periods at an upper end and a lower end. 8. The arithmetic circuit according to claim 1, wherein said first arithmetic circuit and said second arithmetic circuit are provided so as to perform said arithmetic operation on each of two video signals determined from said three primary color signals. By displaying the video signal composed of the output of the video signal and the video signal other than the two video signals defined above, the two video signals identified are determined for a predetermined period of the left end, the right end, the upper end, and the lower end of the screen. 8. The video processing circuit according to claim 7 , wherein the video brightness is reduced. 9. A first arithmetic circuit and a second arithmetic circuit are provided for performing the arithmetic for each of the three primary color signals, and display a video signal composed of an output from each of the arithmetic circuits. By doing, the left edge of the screen,
8. The video processing circuit according to claim 7, wherein the video brightness is reduced during predetermined periods at a right end, an upper end, and a lower end. 10. In the processing of a video signal composed of three primary color signals of a red video signal, a blue video signal and a green video signal each having a predetermined number of bits, the video signal is used for setting a horizontal video display range on a plasma display panel. A first counter that starts counting a predetermined clock signal from the start point of the horizontal display control signal and clears the count at the end point of the control signal; and a first count determined by the first counter. A first decoder that outputs a first decode pulse of a predetermined width when the value reaches a predetermined value, and a first decoder that outputs a first decode pulse having a predetermined width when the count by the first counter reaches a predetermined second count value larger than the first count value. A second decoder that outputs a second decode pulse; and a second decoder that is set by the first decode pulse and outputs the second decode pulse. And a first flip-flop that outputs a first pulse signal of a predetermined width based on the set and reset, and a start of a vertical display control signal for setting a vertical video display range in the plasma display panel. A second counter which starts counting the horizontal synchronizing signal from the point and clears the count at the end point of the control signal; and a predetermined width when the count by the second counter reaches a predetermined third count value. A third decoder that outputs a third decode pulse, and outputs a fourth decode pulse when the count by the second counter reaches a predetermined fourth count value that is larger than the third count value. A fourth decoder, which is set by the third decode pulse,
A second flip-flop that is reset by a decode pulse of the second and outputs a second pulse signal of a predetermined width based on the same set and reset; a first pulse signal from the first flip-flop; A synthesizing unit for synthesizing the second pulse signal from the flip-flop, and performing a logical product operation on the pulse signal from the synthesizing unit and any one of the video signals determined from the three primary color signals; A first arithmetic circuit that outputs a video signal only during the period of the pulse signal, an inverter that inverts the pulse signal from the synthesizing unit, a pulse signal from the inverter, and a video signal other than the determined one video signal A second arithmetic circuit and a third arithmetic circuit for performing a logical sum operation with respect to an arbitrary 1-bit video data in each of them; A logical AND operation is performed on the signal and each of the video signals other than the predetermined bit except for the arbitrary bit in the video signal other than the determined one video signal, and the video signal is output only during the period of the same pulse signal. The fourth provided for each video signal related to the other bits
And the fifth arithmetic circuit are provided, and the video signals from the arithmetic circuits are displayed, so that in the predetermined periods of the left edge, the right edge, the upper edge, and the lower edge of the screen, for one identified video signal, An image processing circuit which does not display an image and lowers the image level of two image signals other than the identified one image signal. 11. A process for setting a horizontal video display range on a plasma display panel in processing a video signal composed of three primary color signals of a red video signal, a blue video signal and a green video signal each having a predetermined number of bits. A first counter that starts counting a predetermined clock signal from the start point of the horizontal display control signal and clears the count at the end point of the control signal; and a first count determined by the first counter. A first decoder that outputs a first decode pulse of a predetermined width when the value reaches a predetermined value, and a first decoder that outputs a first decode pulse having a predetermined width when the count by the first counter reaches a predetermined second count value larger than the first count value. A second decoder that outputs a second decode pulse; and a second decoder that is set by the first decode pulse and outputs the second decode pulse. And a first flip-flop that outputs a first pulse signal of a predetermined width based on the set and reset, and a start of a vertical display control signal for setting a vertical video display range in the plasma display panel. A second counter which starts counting the horizontal synchronizing signal from the point and clears the count at the end point of the control signal; and a predetermined width when the count by the second counter reaches a predetermined third count value. A third decoder that outputs a third decode pulse, and outputs a fourth decode pulse when the count by the second counter reaches a predetermined fourth count value that is larger than the third count value. A fourth decoder, which is set by the third decode pulse,
A second flip-flop that is reset by a decode pulse of the second and outputs a second pulse signal of a predetermined width based on the same set and reset; a first pulse signal from the first flip-flop; A synthesizing unit for synthesizing the second pulse signal from the flip-flop, and a logical product of the pulse signal from the synthesizing unit and any two video signals determined from the three primary color signals. A first arithmetic circuit and a second arithmetic circuit for outputting a video signal only during the period of the pulse signal, an inverter for inverting a pulse signal from the synthesizing unit, a pulse signal from the inverter, A third arithmetic circuit for performing a logical sum operation on an arbitrary 1-bit video data in video signals other than the two video signals, and a pulse signal from the synthesizing unit; A logical AND operation is performed on the video signal of the other bits except for the arbitrary bit in the video signal other than the determined two video signals, and the video signal is output only during the period of the pulse signal. A fourth arithmetic circuit provided for the video signal, and displaying the video signal from each of the arithmetic circuits so that the two video images identified in the predetermined periods of the left end, the right end, the upper end, and the lower end of the screen are displayed. A video processing circuit wherein no video is displayed for a signal, and a video level is lowered for one video signal other than the two identified video signals. 12. The apparatus according to claim 2, wherein the signal counted by said counter is replaced by a horizontal synchronizing signal, and is a horizontal display control signal for setting a horizontal image display range in the plasma display panel.
4, claims 6 to 9, claim 10 and claim 11 video processing circuit according. Wherein said plasma instead of display panel, the video processing circuit of claim 1 to claim 12, wherein it has a liquid crystal display device.