JPH08336090A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: To improve the image display rate while suppressing clock frequency, drive capability and power consumption required for horizontally scanning by simultaneously selecting plural picture elements connected to the same vertical signal lines in a block display area so as to conduct horizontal scanning in the case of displaying an image through aspect conversion. CONSTITUTION: When an input video signal SG31 is displayed while its aspect ratio is converted, a memory means storing information by plural lines is provided and signals SG32 are outputted twice in one horizontal scanning period. Then the stored information is sequentially written on two horizontal picture elements to convert an interlace signal into a noninterlace signal. In a block level display area, plural picture elements connecting the same vertical signal lines are selected simultaneously for horizontal scanning. That is, gates of odd numbered rows and even numbered rows are selected simultaneously for a period (c) of a black level display and a transfer pulse of VSR is sent twice for one horizontal scanning period. For a period (d) of a video display section, gates of odd numbered rows and evened number rows are alternately selected once each for one horizontal scanning period and a transfer pulse of VSR is fed once for the one horizontal scanning period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having an active matrix type liquid crystal display panel and having a function of displaying a video signal having an aspect ratio different from that of a screen.

[0002]

2. Description of the Related Art FIG. 7 shows a system configuration diagram of a liquid crystal display device conventionally used. In the figure, 1 is a TV signal input terminal, 2 is a decoder for converting the TV signal into RGB color signals, and 4 is a liquid crystal driving signal for switching the color-converted signal to forward / reverse in sequence at predetermined intervals. The inversion control and signal amplification unit 5 is a logic unit that forms pulses for inversion control and a liquid crystal panel drive. 6 indicates a liquid crystal panel,
Of these, 7 is a horizontal shift register (HSR), 8 is a vertical shift register (VSR), and 9 is a pixel portion.

FIG. 8 shows a circuit configuration of the display section of the liquid crystal panel 6. In the figure, 7 is the HSR, and 9 is the pixel section, as in FIG. 10 is a thin film transistor, 11 is a liquid crystal, 1
2 is a storage capacitor, 13 is a counter electrode, 14 is a video signal line, 1
5 is an information signal line, 16 is a scanning signal line (gate line), 17
Indicates a signal line selection switch. Further, 71 is an HSR start pulse (HST), 72 is an HSR clock pulse (HCLK), and 81 is a VSR start pulse (VS).
T) and 82 are clock pulses (VCLK) of VSR.

Further, FIG. 9 shows a schematic diagram for explaining scanning lines for applying an interlace signal to be displayed by the liquid crystal display device. In the figure, O _n indicates the _nth row of the odd field, and E _n indicates the _nth row of the even field. In interlaced scanning, even rows are interlaced in odd fields, and then odd rows are scanned in such a manner that the spaces (interlaced rows) are filled in even fields.
Complete one video (one frame) at Hz.

By the way, it is generally said that liquid crystal of TN type or STN type has a response speed of several to several tens of ms. Therefore, if this interlaced scanning is performed on the liquid crystal panel like the CRT, it is not possible to follow the fast movement of the screen and the dynamic resolution is lowered. On the other hand, when the interlaced scanning is performed, the signal writing cycle to the same pixel is 30 Hz, and when the signal polarity inversion is performed so as not to burn the liquid crystal, the liquid crystal signal writing cycle of the same polarity is 15 Hz. Flicker occurs because the human eye is sensitive to flicker of 30 Hz or less due to a decrease in the holding potential of the pixel portion and an asymmetry of the signal with respect to the common electrode (counter electrode) that causes a change in the screen brightness in this cycle. Occurs, resulting in deterioration of image quality.

As a method for solving the problem in such interlaced scanning, even-numbered fields are applied to pixels in the same row (pixels whose gate electrodes are connected to the same scanning signal line) of the liquid crystal panel in which the number of scanning signal lines 16 is halved. There is known a method of writing the n-th signal in the even row and the n-th signal in the odd row in the odd field. Table 1 shows signals written in each field in each horizontal pixel row on the liquid crystal panel at this time. Here, O _n (m) is data obtained by sampling the n-th signal in the odd-numbered row of the interlaced signal of the m-th frame at the timing matched with the pixel array of the panel.

[0007]

[Table 1]

In the above case, the signal writing cycle to the same pixel is 60 Hz, human eyes cannot follow the change in the brightness of the screen, and the deterioration of image quality as flicker does not occur. Moreover, since the entire screen is rewritten at 60 Hz, it is possible to follow a rapid screen change.

In recent years, in addition to video equipment having an aspect ratio of 4: 3 such as NTSC and PAL, 1 like HDTV.
A growing number of devices display images with an aspect ratio of 6: 9. Under these circumstances, the opportunity to display an image having an aspect ratio different from that of the screen of the image display device has increased, and the function of performing the aspect conversion has become popular. For example, 1
FIG. 5A shows a state in which a 6: 9 image is displayed on a screen having an aspect ratio of 4: 3. In this case, a double circle that is originally a perfect circle is an image that extends in the vertical direction. Therefore, the vertical image is compressed to about 3/4, and a black signal or the like is written in the area where the image is lost to perform aspect conversion as shown in FIG. 5B, and a 16: 9 screen display is performed. ing. The video compression in the vertical direction is realized by thinning out ¼ of the information signal transmitted to the information signal line.

Such aspect conversion is also performed in the liquid crystal display device. For example, considering a liquid crystal panel in which the number of scanning signal lines is halved, when displaying a 16: 9 screen such as an HDTV on a screen with an aspect ratio of 4: 3 for NTSC, the display ratio of the screen is P%. Then, in one field = 262.5 lines, the video signal period is 242.
Since there are five, 242.5 x (P / 100) x (1 /
4) Scanning such as thinning is performed for this portion, and the image in the vertical direction is set to 3/4 so as to correspond to a horizontally long 16: 9 screen. At this time, 242.5 × (P
/ 100) × 1/4 non-signal areas are displayed in a constant color such as black. Here, considering the time for writing a signal to the liquid crystal screen, the video signal period is 242.5H × P / 10.
Since the remaining black display area has to be written at a time other than 0 (1H = 63.5 μs, one horizontal scanning period), T ₁ = 262.5H−242.5H × P / 100 A black signal must be written in pixel rows of × (P / 100) × (1/4). If a black signal is written in one pixel row in one horizontal scanning period (1H), T ₁ = 262.5H-242.5H × P / 100> 24
From 2.5H × (P / 100) × 1/4, P <86.6%.

Therefore, in order to perform screen display with a display rate of 86.6% or more, black signals must be written in a plurality of pixel rows within one horizontal scanning period. For this reason, there is known a method of doubling the transfer frequency of the horizontal shift register to scan two consecutive pixel rows in one horizontal scanning period in the area for black display. As a result, the display rate is secured up to P ≦ 96.2%.

[0012]

However, the above-mentioned conventional liquid crystal display device has the following problems.

In the above-mentioned interlaced scanning, when a liquid crystal panel having half the scanning signal lines is used, the apparatus itself can be easily realized at low cost, but the vertical resolution is halved. Therefore, there is a method of using a line memory to interpolate between signals of interlaced fields, convert them into line-sequential scanning signals, and display at 60 Hz. In this case, the writing cycle of the signal to the same pixel is 60 Hz, and the human eye does not follow the change in the brightness of the screen, so that the image quality does not deteriorate as flicker. Moreover, since the entire screen is rewritten at 60 Hz, it is possible to follow a rapid screen change. At this time, the signal writing to the pixel rows of the liquid crystal panel is performed by scanning two rows continuously within one horizontal scanning period to write about 460 to 485 pixel rows in one field = 262.5H period. To realize. Therefore, in order to perform the aspect conversion in the same manner as in the liquid crystal panel in which the scanning signal lines are halved and to secure a sufficient display ratio, the black display area does not scan the pixel rows four times within one horizontal scanning period. must not. This is about 4 horizontal shift registers
It is necessary to move at twice the frequency, and when many pixel transistors are connected such as liquid crystal to drive a large capacity information signal line, the required driving capacity increases, the power consumption increases, and the required basic clock also becomes faster. There is a problem that the load on the logic system also increases.

[0014]

According to the present invention, when an input video signal is aspect-converted and displayed, black is displayed above, below, or above and below the aspect-converted video display area. In the image display device, the memory means for storing information of a plurality of rows is provided, and the stored information is sequentially written into two horizontal pixel rows by outputting a signal twice within one horizontal scanning period. The interlace signal is converted into a non-interlace signal by the above, and a plurality of pixels connected to the same vertical signal line are simultaneously selected in the black display region to perform horizontal scanning, which is a liquid crystal display device. Further, in the present invention, pixel rows to which signals of odd-numbered rows are simultaneously written and pixel rows to which signals of even-numbered rows are simultaneously written are shifted by one row, and in a black display region,
The polarities of the signals to be written are inverted for each pixel row selected at the same time, and the polarities are further field-inverted, and aspect conversion is performed using a plurality of thinning rates.

By adopting the above structure, the present invention has a simple structure, but displays an aspect-converted image with a high image display ratio while suppressing an increase in the clock frequency, driving capability and power consumption required for horizontal scanning. Is possible.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to an embodiment in which a line memory is used to convert an interlaced signal into a non-interlaced signal (continuous double speed signal).

[Embodiment 1] FIG. 4A shows a schematic view of a screen at the time of aspect conversion in the first embodiment of the present invention.

FIG. 10 shows the color arrangement of the pixels of the liquid crystal panel of this embodiment. The pixel arrangement is a mosaic delta arrangement. Therefore, pixels of different colors are connected to the same information signal line of the liquid crystal panel. In addition, since even-numbered rows and odd-numbered rows are arranged such that the horizontal positions of pixels of the same color are shifted by a half cycle (1.5 pixels), sampling is performed by changing the timing for each color signal between even-numbered rows and odd-numbered rows. Do.

FIG. 11 shows a system configuration of a liquid crystal display device using a line memory that realizes serial-in-serial-out using two shift registers for reading and writing. In the figure, 1 is a TV signal input terminal, 2
Is a decoder unit for converting a composite TV signal into an RGB color signal, 3 is an analog line memory unit, 4 is an inversion control and signal amplification unit which sequentially switches the signal to normal / inversion every predetermined period to be a liquid crystal driving signal, Reference numeral 5 is a logic section for forming pulses for memory control, inversion control, and liquid crystal panel driving. Reference numeral 6 denotes a liquid crystal panel, of which 7 is a horizontal shift register (HSR) as a scanning means in the horizontal direction, and 8
Is a vertical shift register (V
SR) and 9 are pixel portions. The interlaced signal input to the input terminal 1 is color-decoded at 2, and then converted to a non-interlaced signal by the analog line memory unit 3, and the liquid crystal panel 6 rewrites the entire screen at a cycle of 60 Hz. At this time, the time series serial signals are input to the line memory for each of the three color signal lines, and the memory output also outputs the time series serial signals for each of the three color signal lines of the liquid crystal. Here, RGB is used in the decoding unit 2.
Although the RGB signals are delayed by different amounts according to the order of the pixel arrangement, the analog line memory unit 3 may be used. This makes it possible to obtain signal information that matches the spatial arrangement of pixels on the liquid crystal with the same sampling pulse, and the frequency of the sampling clock of the memory section and the liquid crystal panel is set to 1/3.

FIG. 12 shows the analog line memory unit 3 described above.
The block diagram of is shown. In the figure, 18 is an input stage of the memory unit, 1
9 is a shift register (WSR) for writing to the memory, 20
Is a start pulse (WST) for WSR, 21-1, 2
1-2 is a two-phase clock pulse for WSR (WCLK1,
WCLK2), 22 is a memory read shift register (RSR), and 23 is a start pulse (RS) for RSR.
T) and 24 are clock pulses (RCLK) for RSR. Reference numeral 25 denotes a switching control unit for switching the signal to be sent to the video signal line according to the color arrangement of the liquid crystal panel. Reference numeral 33 is a sample and hold circuit, and 34 is an input terminal for a sample and hold pulse. 26 is an output stage of the memory section. 27R, 27G and 27B are RGB signal input terminals, and 28A, 28B and 28C are R terminals.
And G, G and B, and B and R are output terminals for switching and outputting with 25 switches in even and odd rows of the liquid crystal screen, and 29 is an input terminal for a switching control signal. 30a to 30f are even rows of liquid crystal screens of RGB colors,
It is a memory column for odd rows, and is alternately distributed from the same horizontal signal every other clock of the shift register 19 for writing.

FIG. 13 shows a concrete example of the structure of the memory array. In the figure, 43A to 43C are switching control units 25 in FIG.
The output line of the memory between the sample hold circuit 33 and the sample hold circuit 33 is shown. In addition, 1 to n of 39a to f represent 1 bit to n bit of each memory column. When the signal is read, the switching control signal 29 causes the signals 39a, 39c, 30e.
Or 30b, 30d, 30f.

FIG. 14 shows the liquid crystal and memory drive timing in the horizontal scanning period. SG1R is a red video signal, SG1G is a green video signal, SG1B is a blue video signal, SG2 is WST, SG3 is WCLK1, SG4 is WCLK2, SG5 is RST, SG6 is RCLK, SG.
7 is a color selection switching signal, SG8A to C are signals converted into line sequential scanning signals output from the memory section, and SG9 is HS.
R start pulse (HST) and SG10 are clock pulses (HCLK) for HSR.

With such a configuration, the serial signals sampled at the double density are taken out alternately, and after being converted into two serial signals rearranged in order to match the pixel arrangement of the liquid crystal screen, While switching to each output terminal, signals for two rows are continuously scanned in one horizontal scanning period by a read shift register that operates with another clock.

Table 2 shows signals to be written in each row (2n to 2 (n + 2)) for each field on the liquid crystal panel.
Here, O _n (m) and O _n '(m) are data obtained by sampling the odd-numbered n-th signal of the interlaced signal of the m-th frame at different timings according to the pixel array of the even-numbered row and the odd-numbered row of the panel. Is.

[0025]

[Table 2]

By rewriting every even field and odd line of the screen for every 1 field (60 Hz), both problems of dynamic resolution and flicker can be solved. Also, when viewed in one field, the resolution in the vertical direction becomes half of that of the original signal, but the display is shifted by one line in the next field to display the pseudo vertical resolution. In this way, the interlaced signal is converted into the non-interlaced signal in the low-cost line memory, and good image quality is realized.

FIG. 1 shows the circuit configuration of the display section of the liquid crystal panel in this embodiment, and FIGS. 2 and 3 show the signals of the respective sections in the vertical drive at this time. Among the reference numerals in the figure, the same reference numerals as those in FIGS. 7 and 8 described above indicate the same parts. In the figure, 14A to C are video signal lines, 71 is an HSR start pulse (HST) terminal, 72 is an HSR transfer clock pulse (HCLK) terminal, 81 is a VSR start pulse (VST) terminal, and 82 is a VSR. This is a transfer clock pulse (VCLK) terminal. Reference numeral 91 is an odd gate selection pulse terminal, and 92 is an even gate selection pulse terminal. Also,
SG31 is an original video signal, SG32 is terminals 28A, B, C
Output signal from the memory, SG33 is VCLK, S
G34 is an odd gate selection pulse, and SG35 is an even gate selection pulse. In FIG. 2, (c) represents the signal period of the black display portion, and (d) represents the signal period of the video display portion.
In the period of the black display portion in (c), the gates in the odd-numbered rows and the gates in the even-numbered rows are simultaneously selected, and the VSR transfer pulse is sent twice in one horizontal scanning period. In the period (d), the gates in the odd-numbered rows and the gates in the even-numbered rows are alternately selected once in each horizontal scanning period, and the VSR transfer pulse is sent once in each horizontal scanning period. In the image period of (d), the image horizontally scanned is thinned out at a ratio of one in four, and the image in the vertical direction is compressed to 3/4.

SG36-1, SG36-2, SG37-
1, SG37-2 represent signals input from the video signal lines 14A, B, C of FIG. In order to drive the liquid crystal so that the liquid crystal does not burn and the flicker cannot be seen, a signal having an inverted polarity is applied to the common electrode of the pixel. Where -1
And -2 represent the signals of the odd field and the even field, SG36-1, SG36-2, SG37-1,
In each of the SG37-2, the polarity is inverted every horizontal pixel row in the video display period of (d), but in the SG36, the signal period of the black display portion of (c) is simultaneously selected and scanned 2 The case where the polarity of the signal is inverted for each row is shown, and in SG37, the period of the black display portion in (c) shows that the polarities of adjacent pixel rows in the same field are the same and are inverted at the field cycle. In any case, since the signal is black, the change in the light transmittance with respect to the signal is small like in the case of a halftone, so that it appears as a line flicker even if the polarity is not inverted every horizontal pixel row like in the video display period. It does not cause deterioration of image quality.

By adopting such a configuration and driving method, four horizontal pixel rows are written in one horizontal scanning period in the black display region, and the scanning time required to secure the effective display rate in the video period is secured. As a result, it is possible to display an aspect-converted image with a high image display rate while suppressing an increase in the clock frequency, driving capability, and power consumption required for horizontal scanning, with a simple configuration.

In a system in which two liquid crystal panels each having 485 horizontal scanning pixel rows are written two in one horizontal scanning period, the image in the vertical direction is set to 3/4, which corresponds to a horizontally long 16: 9 screen. At this time, a constant color display such as black is displayed in the non-signal area of 485 × (P / 100) × 1/4 lines generated on the top and / or bottom of the screen. Here, considering the time for writing a signal on the liquid crystal screen, the video signal period 242.
Since the remaining black display area must be written in a time other than 5H × P / 100 (H = 63.5 μs), T ₁ = 262.5H-242.5H × P / 100 at a time of 485 × (P / 100) × 1/4 horizontal pixel columns, a black signal is written: T ₁ = 262.5H-252.5H × P / 100> (4
From 84/4) × (P / 100) × 1/4, P ≦ 96.2%, and the screen display rate can be secured up to 96.2%.

[Embodiment 2] FIG. 4B shows a schematic view of a screen at the time of aspect conversion in the second embodiment of the present invention. In FIG. 4, (e) is thinned out at a rate of one in four, and (f) is thinned out at a rate of one in eight. The configuration of the drive system using the liquid crystal panel and the memory used here is the same as that of the first embodiment.

FIG. 6 shows a timing chart of the effective image display area in this embodiment. Here, SG41 represents an output signal from the memory, and is read twice in one horizontal scanning period. SG42 is a VSR transfer pulse, SG43 is a gate pulse for odd pixel rows, and SG44 is a gate pulse for even pixel rows. -A shows the timing when the thinning display is performed at a rate of 1 out of 4 lines, and -b shows the timing when the thinning display is performed at a rate of 1 out of 8 lines. 2 from the 2n-1 row at this time in Tables 3 and 4
The signals m _{n to} m ₁₆ in the periods (e) and (f) of FIG. 4B are written in the n + 10 and 12 rows, respectively.

[0033]

[Table 3]

[0034]

[Table 4]

In the first embodiment, T ₁ = 262.5H
The black display area was written in the blanking period of −242.5H × P / 100 to secure the display rate of 96.2% or less. Actually, all the time of the blanking period is written in the pixel portion. Often cannot be assigned to. For example, writing dummy pixels in the display area,
By being used for resetting pixels and signals, the writing time of pixels becomes shorter than T ₁ . Therefore, in order to secure more time, in the present embodiment, the screen is not strictly compressed to 3/4, and the display is performed by changing the thinning rate of a part of the screen area (here, compressed to 7/8). As a result, the black display area is reduced by the amount corresponding to the reduction in the image compression rate, so that the black display area can be written within the remaining time of the blanking period.

[0036]

The liquid crystal display device of the present invention has a simple structure, but displays an aspect-converted image with a high image display ratio while suppressing an increase in the clock frequency, driving capability and power consumption required for horizontal scanning. Is possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a display unit of a liquid crystal panel in a first embodiment of the present invention.

FIG. 2 is a diagram showing signals of respective parts in vertical driving in the first embodiment of the present invention.

FIG. 3 is a diagram showing signals of respective parts in vertical driving in the first embodiment of the present invention.

FIG. 4 is a schematic diagram of a screen at the time of aspect conversion in the second embodiment of the present invention.

FIG. 5 is a diagram showing a state in which a 16: 9 image is displayed on a screen having an aspect ratio of 4: 3.

FIG. 6 is a timing diagram of an effective image display area in the second embodiment of the present invention.

FIG. 7 is a system configuration diagram of a conventional liquid crystal display device.

8 is a diagram showing a circuit of a display section in the apparatus shown in FIG.

9 is an explanatory diagram of scanning lines for applying an interlace signal displayed by the device shown in FIG.

FIG. 10 is a diagram showing a color arrangement of pixels of the liquid crystal panel according to the first embodiment of the present invention.

FIG. 11 is a system configuration diagram of a liquid crystal display device using a line memory that realizes serial-in-serial-out using three shift registers.

12 is a block diagram of an analog line memory of the liquid crystal display device shown in FIG.

13 is a diagram showing a specific configuration example of a memory column of the analog line memory shown in FIG.

FIG. 14 is a diagram showing liquid crystal and memory drive timings in the horizontal scanning period according to the first example of the present invention.

[Explanation of symbols]

 1 TV signal input terminal 2 RGB conversion decoder 3 Analog line memory 4 Inversion control and signal amplification part 5 Logic part 6 Liquid crystal panel 7 Horizontal shift register 8 Vertical shift register 9 Pixel part 10 Thin film transistor 11 Liquid crystal 12 Storage capacitor 13 Counter electrode 14 Video signal Line 15 Information signal line 16 Scanning signal line 17 Signal line selection switch 14A to C Video signal line 71 Start pulse terminal of HSR 72 Transfer clock pulse terminal of HSR 81 Start pulse terminal of VSR 82 Clock pulse terminal of VSR 91 Odd gate selection pulse Terminal 92 Even gate selection pulse terminal

Claims (6)

[Claims] 1. When an input video signal is aspect-converted and displayed, on the aspect-converted video display area,
In an image display device for displaying black outside a video display region that occurs below or above and below, a memory means for storing information for a plurality of rows is provided, and a signal is output twice within one horizontal scanning period, so that the memory By sequentially writing the obtained information to two horizontal pixel rows,
A liquid crystal display device, wherein an interlaced signal is converted into a non-interlaced signal, and a plurality of pixels connected to the same vertical signal line are simultaneously selected in the black display region to perform horizontal scanning. 2. A signal output twice in one horizontal scanning period in the memory means is two pixel rows sampled from the same horizontal scanning signal in accordance with pixel arrays of even rows and odd rows of a liquid crystal panel. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device includes minute data, and the signals of two rows and one set are displayed while being shifted by one pixel row of the liquid crystal panel in the even field and the odd field. 3. The liquid crystal display device according to claim 1, wherein the polarities of signals are field-inverted in the black display region. 4. The liquid crystal display device according to claim 3, wherein in the black display region, polarities of signals written between adjacent pixel rows in the same field screen are the same. 5. The liquid crystal display device according to claim 3, wherein in the black display region, the polarities of the signals to be written are inverted for each pixel row selected at the same time. 6. The liquid crystal display device according to claim 1, wherein the image display area is aspect-converted using a plurality of thinning rates.