JPH02665U - - Google Patents
Info
- Publication number
- JPH02665U JPH02665U JP4985689U JP4985689U JPH02665U JP H02665 U JPH02665 U JP H02665U JP 4985689 U JP4985689 U JP 4985689U JP 4985689 U JP4985689 U JP 4985689U JP H02665 U JPH02665 U JP H02665U
- Authority
- JP
- Japan
- Prior art keywords
- row
- circuit
- column
- data
- rows
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Description
第１図はｈ列ｖ行に分割した画面を示した説明
図、第２図は従来の回路構成例を示したブロツク
図、第３図は第２図の構成によつて表示される波
形の例を示した説明図、第４図は本考案の一実施
例を示したブロツク図、第５図は本考案によつて
表示される画素の位置を示した説明図、第６図は
第３図と同じ波形を第４図の構成によつて表示し
た波形を示す説明図である。
Ｍ……記憶回路、ＶＣ……行指定回路、ＨＣ…
…制御回路、ＤＬ……遅延回路、ＣＭ……比較回
路、Ｄ……ＣＲＴ表示装置。
Fig. 1 is an explanatory diagram showing a screen divided into h columns and v rows, Fig. 2 is a block diagram showing an example of a conventional circuit configuration, and Fig. 3 is an illustration of a waveform displayed by the configuration of Fig. 2. FIG. 4 is a block diagram showing an embodiment of the present invention, FIG. 5 is an explanatory diagram showing the positions of pixels displayed by the present invention, and FIG. FIG. 5 is an explanatory diagram showing a waveform that is the same as that shown in the figure and is displayed using the configuration shown in FIG. 4; M...Memory circuit, VC...Row designation circuit, HC...
...Control circuit, DL...Delay circuit, CM...Comparison circuit, D...CRT display device.
Claims (1)
３，……）行の画素に分割し、各行を走査して波
形表示を行う表示装置において、 各列に対応してアドレスを設定してあり、各ア
ドレスにはその列における波高値に対応した行を
データとして記憶する記憶回路と、 画面上で走査されている行を指定する行指定回
路と、 この行指定回路によつて一つの行が指定される
ごとに、行走査に同期して上記記憶回路の全デー
タを順次読み出す制御回路と、 上記行指定回路によつて指定された行が、上記
記憶回路から現在読み出されているデータに対応
した行とその前に読み出されたデータに対応した
行との間に位置するとき上記データの読出しに伴
つて画素表示信号を生じる比較回路とからなり、 各列において、その列における波高値に対応し
た行と、前列における波高値に対応した行との間
に位置する画素を全て表示する ことを特徴とする波形表示装置。[Scope of claim for utility model registration] The screen is divided into h (h=2, 3,...) columns v (v=2,
In a display device that displays waveforms by dividing pixels into rows (3,...) and scanning each row, an address is set corresponding to each column, and each address has a value corresponding to the peak value in that column. A memory circuit that stores rows as data, a row designation circuit that designates the row being scanned on the screen, and each time a row is designated by this row designation circuit, the above operations are performed in synchronization with the row scanning. A control circuit that sequentially reads out all data in the memory circuit; and a control circuit that causes the row specified by the row designation circuit to be divided into a row corresponding to the data currently being read from the memory circuit and data read before that. It consists of a comparator circuit that generates a pixel display signal when the above data is read when located between the corresponding row, and in each column, a comparison circuit that corresponds to the peak value in that column and a comparison circuit that corresponds to the peak value in the previous column. A waveform display device characterized by displaying all pixels located between rows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4985689U JPH02665U (en) | 1989-04-27 | 1989-04-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4985689U JPH02665U (en) | 1989-04-27 | 1989-04-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02665U true JPH02665U (en) | 1990-01-05 |
Family
ID=31275937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4985689U Pending JPH02665U (en) | 1989-04-27 | 1989-04-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02665U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4833870A (en) * | 1971-09-03 | 1973-05-14 | ||
| JPS5011071A (en) * | 1973-05-29 | 1975-02-04 |
-
1989
- 1989-04-27 JP JP4985689U patent/JPH02665U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4833870A (en) * | 1971-09-03 | 1973-05-14 | ||
| JPS5011071A (en) * | 1973-05-29 | 1975-02-04 |
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