JPH0623793B2 - Luminance interpolation method for raster scanning waveform display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention sequentially samples an input signal waveform and stores it in a bit map memory, and reads this memory in the time axis address direction in correspondence with raster scanning. The present invention relates to a brightness interpolation method for connecting adjacent sampling data by dots in a raster scanning waveform display device that displays a dot pattern waveform.

[Conventional technology]

In order to increase the resolution in the time axis direction in this type of device, it is necessary to increase the writing / reading speed of the bitmap memory and the speed of its luminance interpolation processing in response to the increase in sampling speed.

[Problems to be Solved by the Invention]

However, such speeding up increases the cost of the bitmap memory or the luminance interpolating circuit, and also has a technical limit.

Therefore, it is an object of the present invention to provide a brightness interpolation method for a raster scanning waveform display device that can also perform brightness interpolation in a state where the resolution in the time axis direction can be improved without increasing the operation speed of the bitmap memory. And

[Means for solving problems]

In order to achieve this object, the present invention sequentially samples an input signal waveform, stores amplitude data of each sampling period for at least one display surface in a memory, and sequentially reads from this memory every sampling period. The first dot data linearly interpolated so as to connect with the adjacent amplitude data is sequentially created, and the same is applied to the amplitude data group of the remaining one sampling cycle read in sequence from the memory. The second dot data linearly interpolated so as to connect with the adjacent amplitude data is sequentially created, and the first and second dot data are respectively converted into the first and second dot map data corresponding to the display surface. Store in the bitmap memory, and set the first and second bitmap memories to 1/2 the sampling speed in the time axis address direction.
At the same time, the dot data of the first and second dot data, which is later in time, is delayed by one sampling period to generate a logical sum of both dot data as a video signal. Is displayed on the raster scanning type waveform display device in accordance with the raster scanning corresponding to the reading in the time axis address direction.

The matching by the delay of the data time series is performed by adding a delay circuit to the output signal of the memory on the side that is later in time when the both bitmap memories are read at the same time, or delaying the read timing of this memory. It is possible to make it happen.

[Action]

As shown in FIG. 1, the sampling cycle ... T _n , which is sampled by the sampling circuit for the input waveform signal A,
_{T n + 1, T n +} 2, T n + 3, T n + 4 ... amplitude data for ... D _n, D
_{n + 1} , D _{n + 2} , D _{n + 3} , D _{n + 4} ... (A in the figure) are sequentially stored in the memory. Then, as shown in FIG. 7B, the dot data creating means reads out the amplitude data of the sampling cycle of each one ... T _n , T _{n + 2} , T _{n + 4,} ... The first dot data which is linearly interpolated so as to connect between and is sequentially created, and the linear interpolation is similarly performed for the remaining amplitude data groups of sampling intervals of every other unit ... T _{n + 1} , T _{n + 3} . The second dot data is sequentially created and stored in the first and second bitmap memories.

By simultaneously reading and delaying the dot data stored in both bit map memories, or by reading with delay, the logical sum of both dot data is a raster scanning waveform as a time-series video signal corresponding to sampling. It is supplied to the display device and displayed as shown in FIG.

By the way, the solid line or dotted line in FIG. 7D shows the dot pattern waveform in which the luminance is interpolated by the conventional method. Not only is the waveform improved, but the waveforms in which the luminance is interpolated between the data of one unit are vertically adjacent to each other, so that the waveform becomes smooth.

〔Example〕

FIG. 2 shows a circuit configuration of a brightness interpolation method for a raster scanning type waveform display device according to an embodiment of the present invention.

In the figure, 10 is a sampling pulse generation circuit for generating a sampling pulse S _o , and 11 is a time-axis address advance signal S which is obtained by dividing the sampling pulse S _o by half.
And a switching circuit 12 that alternately switches and outputs the sampling signal in synchronization with the sampling pulse S _o .

A sampling circuit 13 sequentially samples the analog input waveform A in synchronization with the sampling pulse S _o and holds it. The switching circuit 12 supplies the amplitude data group of every other sampling period to the CRT display device 14.
It is a static RAM that stores almost one display surface of 23. Numeral 14a is a static RAM which is supplied with the remaining amplitude data group of every other sampling period by the switching circuit 12 and similarly stores approximately one display screen of the cathode ray tube display device 23.

Reference numeral 15 denotes a latch circuit which sequentially reads and holds the amplitude data of each time axis address of the SRAM 14 in synchronization with the time axis address step signal S. Reference numeral 15a is a latch circuit that sequentially holds the amplitude data held by the latch circuit by delaying it by one cycle of the time axis address advance signal S. Reference numeral 16 is a counter which sequentially counts the clock K having a frequency higher than the cycle of the time axis address step-up signal S, and outputs a coincidence signal when the count value coincides with the preset held value of the latch circuit 15. 16a is also a counter that presets the value held in the latch circuit 15a and performs the same operation. A flip-flop circuit 17 is set and reset by the coincidence signals output from the counters 16 and 16a, and sets the serial dot data SD to "1" while these coincidence signals are generated.

18 is a multi-port dynamic RAM (Hitachi HM53461-12) group as a bit map memory. This D
The RAM is capable of writing serial dot data by a clock shift operation in a direction orthogonal to the read direction. In addition, the middle address A _M of the amplitude direction address
The divided upper area 18 _U (composed of one or more DRAMs according to the memory capacity) and lower area 18 _D (also one or more similarly) can be set to write and read modes independently. Has become. _18a is a similar DRAM.

Reference numeral 19 denotes a memory control circuit, which receives the horizontal synchronization signal HSYNC as an input and the DRAM 18, 1 at every raster scanning time of 1/2 display surface.
8 _a sets the upper region 18 _U and a lower region 18 _D alternately read and write mode, first display surface in a raster scanning time written in one display surface portion of region CRT display device 23 of SRAM14 Read it twice.

Reference numeral 20 is a serial dot data creating means for the remaining sampling signals at the intervals of one sampling period, which is composed of the above-mentioned respective units 15, 15a, 16, 16a, 17 and is supplied from the switching circuit 12. 21 indicates both DRs that are read and scanned at the same time
It is a delay circuit that delays the output signal of the DRAM 18a storing the serial dot data of the later sampling period of AM18 and 18a by one sampling period. 22 is an OR gate that receives both video signals. The cathode ray tube display device 23 sequentially reads out the read mode area of the DRAM 18 in the time axis address direction and displays a waveform by raster scanning.

The operation of the CRT waveform display device configured as described above is as follows.

Sampling signal of the input analog waveform A is sampled by the sampling circuit 13 sequentially are alternately stored in the SRAM14 or SRAM14a for each input of the sampling pulse S _o. The memory control circuit 19, for example DRAM18,18a the upper region 18 _U sets a read mode and a lower region 18 _D in write mode, double write the written area of the first display surface portion of SRAM14,14a Read at the speed of.

The one-side latch circuits 15 and 15a sequentially hold the amplitude data of the adjacent time-axis addresses of one pair. As a result, the flip-flop circuit 17 supplies the serial dot data SD ₁ that sets “1” between both dot data, that is, between the coincidence signals to the DRAM 18. And the upper area 18 _U
While reading scanning is performed, with respect to the lower region 18 _D, and sequentially by incrementing the amplitude addresses for each input of the clock K for each time axis address during the next time-axis address increment signal S is generated Serial dot data SD ₁ is written at high speed. In this way, when the writing of all time-axis addresses up to the intermediate address A _M is completed, the same memory content is read again from the next area of SRAM 14, and conversely the upper area 18
Performs writing of _U, causes the reading of the lower region 18 _D.

For example, in FIG. 3, the sampling period ... T _{n to} T _{n + 4}
For dot data including data crossing the upper and lower sides of the intermediate address A _M ... D _{n to} D _{n + 4} (a in the figure), the upper area 18 _{U of the} DRAM 18 is during the read mode, with respect to the lower region 18 _D, intermediate address a _M serial dot data ... SD _1n up, SD _{1n + 1} ... is written, by the upper region 18 _U is a read mode, Even if this serial dot data is generated, it is not written. Then, while the lower region 18 _D in the read mode, again the serial dot data ... SD _1n, even SD _{1n + 1} ... is generated, not written until intermediate address A _M, the upper region 18
Only written in _U. In this way, the upper area 18 _{U of the} DRAM 18 is
And the lower area _18D are alternately controlled to be written and read. Similarly, the serial dot data creating means 20 also creates serial dot data ... SD _2n ...
Written to AM18a. Then, the dot data read at the same time as the DRAM 18 is delayed in the delay circuit 21 and combined in a time series corresponding to sampling in the OR gate 22, and in the cathode ray tube display device 23, as shown in FIG. The linearly interpolated high-resolution waveform data is displayed next to each other in the amplitude direction.

As described above, according to this embodiment, the serial dot data in which the luminance of the sampling points of the input waveform is linearly interpolated is created by a simple hardware circuit without using a microprocessor, and the bitmap memory is directly synchronized with the clock. Can be written to. Therefore, the dot map data can be created and written easily and at high speed.

In the above-described embodiment, one static memory may be provided, and a switch circuit may be subsequently provided to alternately supply the amplitude data to the latch circuits of both pairs.
Further, when the analog input signal is a plurality of channels, the above-mentioned pair of SRAMs and dot data generating means are prepared by the corresponding number, and serial data of each flip-flop circuit is supplied to each pair of DRAMs through the OR gate. To configure.

In the case where two display screens of bitmap memory having a capacity corresponding to one cathode ray tube display screen are prepared instead of the above-mentioned one group of DRAMs, the memory control circuit alternately sets both bitmap memory to the read and write modes, At the time of writing, serial dot data can be written from address 0 of the amplitude address to the maximum address for each time axis address. In this case, the SRAM can be read at the same speed rather than twice as much as the bitmap memory. If the circuit configuration becomes complicated, in order to match the time series, instead of using the delay circuit described above, the reading of one of the bitmap memories is delayed by a half cycle of the time axis address step. It is also conceivable to use a memory of a system in which the data is read out and the bitmap memory is written while addressing according to the conventional method.

〔The invention's effect〕

As described above, according to the present invention, it is possible to improve the resolution in the time axis direction after performing the luminance interpolation without increasing the clock speed of the linear interpolation and the dot map memory correspondingly while the sampling speed is improved. . In addition, the displayed waveform becomes smooth because the overlapping portion is increased as compared with the stepped shape.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a diagram for explaining the configuration of a circuit example for implementing the luminance interpolation method of the present invention, and FIG. 3 is for the same embodiment. It is a figure explaining operation.

Claims (1)

[Claims] 1. An input signal waveform is sequentially sampled to store amplitude data of each sampling cycle for at least one display surface in a memory, and the amplitude data group of one sampling cycle read from the memory in sequence. The first dot data linearly interpolated so as to be connected to the adjacent amplitude data is sequentially created, and the amplitude data groups of the remaining one sampling cycle that are sequentially read out from the memory are similarly adjacent to each other. The second dot data linearly interpolated so as to be continuously connected to the amplitude data are sequentially created, and the first and second dot data are first and second dot map data corresponding to the display surface, respectively. 2 dot map memory, and these first and second bit map memories are sampled in the direction of time axis address. Read with 1/2 of
The dot data, which is later in time than the first and second dot data, is delayed by one sampling period to generate a logical sum of both the dot data as a video signal. A luminance interpolation method for a raster scanning type waveform display device, which is characterized by displaying on a raster scanning type waveform display device in accordance with raster scanning corresponding to reading in an address direction.