JPH0623792B2 - Luminance interpolation type waveform display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention sequentially samples an input waveform signal, and bitwise does not connect dots between adjacent sampling data of time-axis addresses for linear luminance interpolation. The present invention relates to a luminance interpolation type waveform display device for displaying a dot pattern waveform by storing it in a map memory and reading the memory in the time axis address direction in correspondence with raster scanning.

[Conventional technology]

According to this type of device, it is possible to repeatedly display a specific region of the input waveform signal. However, when writing dot waveform data with linear brightness interpolation to a conventional bitmap memory, the interpolation data is created by CPU processing and once stored in the memory, then the corresponding address is assigned to the bitmap memory and transferred. Was.

[Problems to be Solved by the Invention]

Therefore, the circuit processing is complicated and the processing time is long.

Therefore, the present invention performs the luminance interpolation with a simple circuit configuration,
Moreover, it is an object of the present invention to provide a luminance interpolation type waveform display device which can be easily written in a bit map memory.

[Means for solving problems]

In order to achieve this object, the present invention uses, as a bit map memory, a memory which is known per se and which can write binary data by sequentially shifting each binary data in the reading direction and the orthogonal direction at each clock input. Assuming the first
It was constructed as shown in the figure. In other words, the input waveform signal is sequentially sampled by the sampling circuit 1 and the memory 2 that stores the amplitude data for the time axis address corresponding to the display surface is stored.
And serial dot data creation means for creating serial dot data for a predetermined number of amplitude addresses in a direction orthogonal to the time axis address direction on the display surface, sequentially for each time axis address, in synchronization with the clock, By sequentially reading the adjacent time axis address amplitude data from 2, the serial dot data creating means 3 is connected by dot data so as to linearly interpolate the amplitude data between these amplitude data, and the serial dot data is assigned to the associated time. Bit map memory 4 corresponding to the display surface, and two areas having at least two areas in which each amplitude address of the axis address can be written while being shifted in synchronism with clock input, and can be simultaneously set in the read mode and the write mode. One of them is set to read mode and the other is set to write mode at the same time. It includes a memory control unit 5 for switching alternately set, the bit map memory into the time-axis address directions is read sequentially and a waveform display unit 6 for displaying on the display surface by raster scanning.

[Action]

As shown in FIG. 2, the time axis address ... Tn sampled by the sampling circuit 1 for the input waveform signal A,
Amplitude data for T _{n + 1} , T _{n + 2} ... D _n , D _{n + 1} , D _{n + 2} ...
(A in the figure) is sequentially stored in the memory 2. The serial dot data creating means 3 uses the amplitude data of adjacent time-axis addresses ... D _n , D _{n + 1} , D _{n + 2} ... To the time-axis address ... T _n ,
T _{n + 1} ... serial dot data ... SD _n shown in synchronism with the drawing b in the clock with respect to create SD _{n + 1} ... sequential. Then, the memory control means 5 causes one area of the bit map memory 4 to be read out in the time axis address direction corresponding to the raster scanning, and at the same time, the other area is orthogonal to each amplitude address in synchronization with the clock. Sequential writing in the direction.
When reading and writing of the respective areas are completed, writing and reading are performed instead.

As a result, the display device 6 displays the waveform of the dot pattern in which the luminance is linearly interpolated by raster scanning, as shown at the same time c.

〔Example〕

FIG. 3 shows a circuit configuration of a luminance interpolation type waveform display device according to an embodiment of the present invention.

In the figure, reference numeral 11 denotes a sampling circuit, which sequentially samples the input waveform signal A in synchronization with the time-axis address advance signal S and holds it. The reference numeral 12 indicates the sampled amplitude data in the cathode ray tube of the cathode ray tube display device 18.
It is a static RAM that stores only the display screen.

Reference numeral 13 denotes a latch circuit which sequentially reads and holds the amplitude data of each time axis address of the SRAM in synchronization with the time axis address advance signal S. Reference numeral 13a is a latch circuit which sequentially holds the amplitude data held by the latch circuit by delaying the time axis address advance signal S by one cycle. Reference numeral 14 is a latch circuit that sequentially counts a clock K having a frequency higher than that of the time-axis address advance signal S and presets a calculated value.
It is a counter that outputs a match signal when it matches the held value of 13. 14a is also a counter that presets the value held by the latch circuit 13a and performs the same operation. 15 is counter 14,
This is a flip-flop circuit that is set and reset by the coincidence signal output from 14a, and changes the serial dot data SD from "0" to "1" between these one coincidence signal and the other coincidence signal. These respective units 13, 13a, 14, 14a, 15 constitute the serial dot data creating means of the present invention.

16 is a multi-port dynamic RAM composed of a plurality of bit map memories (Hitachi HM53461-
12). In this DRAM, serial dot data SD can be written by a clock shift operation in a direction orthogonal to the read direction. Also, the intermediate address of the amplitude direction address
Upper area 16 _U (composed of one or more DRAMs depending on memory capacity) and lower area 16 divided into two on the upper and lower sides by A _M
D (similarly, one or a plurality of _D's ) can be independently set to the write and read modes.

Reference numeral 17 denotes a memory control circuit, which receives the horizontal synchronizing signal HSYNC as an input and alternately switches the upper area 16 _U and the lower area 16 _D of the DRAM 16 to a read / write mode at every raster scanning time corresponding to 1/2 of the display screen. At the same time as the setting, one written area of one screen of the SRAM 12 is read twice during the raster scanning time of one CRT display screen. In addition, this memory control circuit can be used by the SRAM12 to display certain static waveforms.
Is suspended and the serial dot data is created by repeatedly reading from the same written area.

The cathode ray tube display device 18 sequentially reads out the read mode area of the DRAM 16 in the time axis address direction and displays a waveform by raster scanning.

The operation of the CRT waveform display device configured as described above is as follows.

The input waveform signal A sampled by the sampling circuit 11 is sequentially stored in the SRAM 12 for two screens. The memory control circuit 17 sets, for example, the upper area 16 _{U of the} DRAM 16 in the read mode and the lower area 16 _D in the write mode, and also the SRAM.
The 12 written areas for one display screen are read at a speed twice as fast as writing. In the latch circuits 13 and 13a,
Amplitude data of time axis addresses that are successively adjacent to each other are held. As a result, the flip-flop circuit 15 supplies the serial dot data SD that sets the matching signals to “1” to the DRAM 16. Then, while the upper area 16 _U is being read and scanned, the lower area 16 _D is generated while the next time axis address step signal S is being generated. The serial dot data SD is written at high speed. In this way, when the writing of all time-axis addresses up to the intermediate address A _M is completed, the same memory content is read again from the next area of SRAM 12, and conversely, the upper area 16 _U is written, and the lower area is written. 16 to perform the reading of _D.

For example, in FIG. 4, time axis address ... T _n and T _{n + 1}
The data ... D _n and D _{n + 1} (a in the figure) are intermediate addresses
When crossing the upper and lower sides of A _M , as shown in Figure b,
While the upper region 16 _U in read mode, with respect to the lower region 16 _D, serial dot data to an intermediate address A _M ... SD
_n , SD _{n + 1} ... Are written and the upper area 16 _U is not written even if this serial dot data is generated due to the read mode. Next, while the lower region _16D is in the read mode, the serial dot data ... SD _n , SD
_{Even if n + 1} ... Occurs, the intermediate address A _M is not written, but only the upper region 16 _U. DRAM16 like this
By alternately writing and reading control of the upper area 16 _U and the lower area 16 _D , the cathode ray tube display device 18 displays waveform data obtained by linearly interpolating the sampling waveform, as shown in FIG.

In the above-mentioned embodiment, when the analog input signal is a plurality of channels, the corresponding number of SRAMs and serial dot data creating means are prepared and the serial dot data of each flip-flop circuit is DR through the OR gate.
Configure to feed AM16. The waveform display position can be adjusted by providing the counters 14 and 14a with a circuit for adding the holding values of the latch circuits 13 and 13a and the vertical position values.

In addition, when two display screens of bitmap memory with a capacity equivalent to one CRT display surface are prepared, the memory control circuit alternately sets both bitmap memories to the read and write modes, and at the time of writing, each time axis address is set. The serial dot data can be written sequentially from address 0 of the amplitude address to the maximum address. In this case, SRAM can be read at the same speed rather than twice as much as bitmap memory.

〔The invention's effect〕

As described above, according to the present invention, serial dot data linearly interpolated between sampling points of an input waveform is created by a simple hardware circuit without using a microprocessor, and the bitmap memory is directly synchronized with the clock. Can be written to. Therefore, the dot map data can be created and written easily and at high speed.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the configuration of the present invention, FIG. 2 is a diagram for explaining the operation thereof, FIG. 3 is a diagram for explaining the configuration of a linear interpolation device according to an embodiment of the present invention, and FIG. It is a figure explaining operation | movement of an Example.

Claims (1)

[Claims] 1. A memory for storing the amplitude data of each time axis address corresponding to a display surface by sequentially sampling an input waveform signal, and a predetermined amplitude address in a direction orthogonal to the time axis address direction on the display surface. Serial dot data creating means for creating several serial dot data for each time axis address sequentially in synchronization with a clock, by sequentially reading amplitude data of adjacent time axis addresses from the memory, The serial dot data creation means for connecting the dot data so as to linearly interpolate the amplitude data between these amplitude data, and the serial dot data at each amplitude address of the associated time axis address in synchronization with the clock input. It is possible to write while shifting and at the same time to set the read mode and write mode at the same time. A bit map memory having two areas and corresponding to the display surface; memory control means for simultaneously setting one of the two areas to a read mode and the other to a write mode, and alternately switching between these modes; And a waveform display device for sequentially reading the map memory in the time axis address direction and displaying on the display surface by raster scanning.