JP2006133114A - Waveform display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a waveform display device which has no misread of signal waveform, can accelerate updating of waveform representation and achieve real time display causing no dead time. <P>SOLUTION: The waveform display device has bitmap memories A and B. A memory controller 61 writes digital waveform data taken from an AD converter 2 at every frame period in the memory A or the memory B by turns. The written waveform data is read out in the frame period when writing operation of waveform data in the memory A or the memory B is not done. The read-out data is made an image data as it is and the waveform is indicated on the display 5. Writing in the memory A or the memory B in each frame period is initiated at every trigger signal input to the memory controller 61 and the waveform data of the memory length of memories A and B is written in. When data is read out as raster from the memory A or the memory B at every frame period in turn, an image data for one picture is produced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a waveform display device that displays a signal waveform of an input signal, and more particularly, to a waveform display device that can display a signal waveform of an input signal in real time without missing a waveform in the input signal.

  Conventionally, when measuring a signal waveform of an analog input signal, a digital storage oscilloscope (DSO) has been used. The configuration of this DSO is shown in FIG.

  In FIG. 12, the outline of the DSO is shown in a block configuration. The DSO is an input amplifier 1, an analog-digital (AD) converter 2, an acquisition memory 3, a display control unit 4, a display 5 such as a liquid crystal display. A memory control unit 6 and a central processing unit (CPU) 7.

  An analog input signal to be measured is input to the input amplifier 1, where it is amplified and input to the AD converter 2. Although not shown in FIG. 12, the AD converter 2 digitizes the input signal in accordance with a clock signal from a clock oscillator provided in the apparatus. The memory control unit 6 that performs time-base control uses the trigger signal as a base point and outputs the output of the AD converter 2 according to the sweep rate and delay time set on an operation panel (not shown) provided in the apparatus according to the acquisition memory 3. Specifies the memory address to be stored in

  Thereby, the output data of the AD converter 2 is sequentially stored in the acquisition memory 3. FIG. 13 shows how output data is stored. In FIG. 13, the storage area of the acquisition memory is schematically shown, and the output data D1, D2,... Of the AD converter 2 are sequentially stored according to the addresses indicated by the horizontal arrows. This output data is composed of, for example, 8 bits and indicates data corresponding to the vertical axis (Y axis) on the display screen of the display 5. The address here is specified by the memory control unit 6.

  The output data stored in the acquisition memory 3 is transferred to a display memory provided in the display control unit 4 under the control of the CPU 7. Here, the output data stored in the acquisition memory 3 is converted into a format that can be displayed on the display 5 by the display memory, and the content stored in the display memory 5 is displayed in a waveform on the display screen of the display 5. The

  By the way, in the above-described conventional DSO, an analog input signal is converted into digital waveform data, and sequentially stored in the acquisition memory 3 as shown in FIG. 13, and a waveform representing the input signal based on the stored waveform data is generated. Displayed on the display 5. Here, the digital waveform data of the input signal is stored in the acquisition memory 3 based on the trigger signal. In this storage operation, the memory write operation is started in response to the write start signal, and the write is stopped in response to the next trigger signal. Immediately thereafter, a read operation from the acquisition memory 3 is started, and the waveform data is sequentially read and displayed as a waveform. After the read operation for a predetermined period, the write operation starts again in response to the write start signal. If the above operation is repeated and the input signal is a repetitive signal, a stable waveform can be displayed based on the trigger signal.

  However, as described above, the write operation and the read operation of the acquisition memory 3 are executed alternately, and thus the digitization of the input signal and the write operation cannot be performed during the read operation. Accordingly, it becomes impossible to capture the state of the input signal during the readout period, and there arises a problem that not only the capture probability becomes extremely low but also the update of the display waveform becomes slow. For this reason, conventionally, a plurality of memories are used, and one memory performs a write operation to another memory during a read operation to eliminate information capture omission. However, the configuration and control are complicated. was there.

  Therefore, a waveform display device that has improved such problems has been proposed (see, for example, Patent Document 1). In this waveform display apparatus, an AD converter sequentially generates real-time waveform data representing values at a plurality of points of an input signal for a predetermined period with reference to a trigger signal repeatedly generated according to the input signal, and the AD conversion. In response to the waveform data from the device, the waveform data for one cycle of the input signal is repeatedly overwritten in the bitmap memory corresponding to the acquisition memory for each trigger signal. Even during the period when the waveform data is written in the bit map memory, the waveform representing the input signal is displayed according to the waveform data from the bit map memory.

JP-A-3-243863

  By the way, in the waveform display device proposed in Patent Document 1, the bitmap memory starts a write operation in response to a write start signal from the memory control unit, and the address is reset every time a trigger signal is generated. Data is overwritten. As described above, during the period in which the stored contents of the bitmap memory are not erased and the overwriting is repeated, the input signal is always captured according to the clock signal, and the input signal is not captured.

  After the write operation is repeated for a predetermined period set by the user, a write period is provided to stop the write operation by the first trigger signal and transfer the waveform data stored in the bitmap memory to the display memory. Further, an erasing period for erasing all the contents of the bitmap memory is also provided thereafter. Immediately thereafter, the write operation is started again in response to the write start signal, and the same operation is repeated thereafter.

  In the waveform display device disclosed in Patent Document 1, the accumulated waveform of the input signal can be simultaneously displayed on the display unit even during the write operation to the bitmap memory, and the period from the start of writing to the transfer operation of the waveform data is set sufficiently long. As a result, it is possible to increase the possibility of capturing an abnormal waveform with a very low frequency of occurrence.

  However, the waveform display device disclosed in Patent Document 1 needs to be transferred from the bitmap memory to the display memory, and there is a problem that the configuration and control for that purpose are complicated. Further, when the waveform data writing operation to the bitmap memory is repeated, a transfer period for transferring the waveform data to the display memory and an erasing period for erasing all the contents of the bitmap memory must be provided. Due to the presence of these transfer periods and erase periods, a dead time on waveform display occurs, and the occurrence of this dead time is an obstacle to real-time display.

  Therefore, the present invention eliminates the loss of the signal waveform, speeds up the update of the waveform display, realizes real-time display without causing any dead time, and further displays luminance information by an external signal. An object is to provide a waveform display device that can be realized.

  In order to solve the above-described problems, in the waveform display device of the present invention, waveform data generating means for digitizing an input signal to generate waveform data, and display for displaying a signal waveform as an image based on the generated waveform data Each of the first and second storage means in the bitmap format capable of storing the waveform data for each frame period, and each of the first and second storage means, The write operation and the read operation of the waveform data of the written frame period are alternately repeated, and the waveform data for each frame period is displayed on the image in the first storage means or the second storage means. Are written in association with the horizontal axis and the vertical axis of the bitmap, and the waveform data of the frame period is alternately written from the first storage means and the second storage means. Sequentially reads out and outputs the waveform data read the said indicator, and a control means for displaying an image of the signal waveform.

  When the waveform data is alternately written into the first storage unit and the second storage unit for each frame period, the control unit performs the image processing according to a trigger signal generated during the frame period. The waveform data corresponding to one displayed image is written in the first storage means or the second storage means.

  The control means overwrites the waveform data corresponding to one image of the image display in the first and second storage means for each of a plurality of trigger signals generated during the frame period, and further, the image When overwriting the waveform data corresponding to one displayed image in the first and second storage means, the waveform data value corresponding to the dot in the image written in the first and second storage means is read out The waveform data value to be overwritten on the waveform data is added and written as waveform data corresponding to the dot.

  In addition, when the control means overwrites the waveform data corresponding to one image of the image display in the first and second storage means, the control means in the image written in the first and second storage means The waveform data value corresponding to the dot is read out, and a predetermined value is subtracted from the waveform data value and written as waveform data corresponding to the dot.

  In the waveform display device, the waveform data generation means digitizes the first and second input signals to generate first and second data, respectively, and the control means converts the first data to the horizontal axis. The waveform data associated with the dots of the image related to the image display is written in the first and second storage means, with the second data as the coordinate value of the vertical axis.

  The control means can limit the writable period of the waveform data to the first and second storage means for each frame period in accordance with the display state of the signal waveform, and the writable The length of the period can be changed for each frame.

  Further, the waveform data generating means digitizes a third input signal to generate third data, and the control means changes the added value of the third data for each waveform data to change luminance. Modulation can be performed.

  As described above, with the configuration of the waveform display device according to the present invention, digitized waveform data is directly written in the bitmap format alternately in the first storage means and the second storage means, Since the written waveform data is displayed as it is, the acquisition memory is not used, and no display memory is required in the control means. Such control and control for waveform display can be simplified.

  The waveform data is directly written on the memory in the form of a waveform display image, and the next trigger signal is waited immediately after the waveform data is written without waiting for control processing by software for waveform display. Therefore, the waveform display can be updated at high speed, and the display state on the analog oscilloscope can be brought close to the digital oscilloscope. In addition, since the waveform data write operation and read operation can be executed alternately by the first storage means and the second storage means without any breaks, real-time display can be realized without causing any dead time.

  In the waveform display device of the present invention, first and second data obtained by digitizing the first and second input signals are generated, the first data is used as the coordinate value of the horizontal axis of the display image, and the second Since the waveform data is written in the first and second storage means in association with the dot of the image related to the image display as the coordinate value of the vertical axis, the trigger signal serving as the writing base point is not necessary and directly Thus, the waveform display image is written into the memory, and the control related to the waveform data writing operation and reading operation and the control for waveform display can be simplified. Moreover, the waveform display is not interrupted by the memory length, and gradation display can be realized.

  Further, third data obtained by digitizing the third input signal is generated together with the first and second data based on the first and second input signals, and the third data is generated for each waveform data based on the first and second data. By adding the values obtained by the above, it is possible to perform luminance modulation on the waveform data by an external input signal.

  Next, embodiments of the waveform display device of the present invention will be described with reference to the drawings. FIGS. 1 to 7 show a first embodiment of the waveform display device of the present invention, and FIGS. 8 to 11 show a second embodiment of the waveform display device of the present invention.

  First, in FIG. 1, a schematic configuration of the waveform display device according to the first embodiment is shown in blocks. The waveform display device of this embodiment includes an input amplifier 1, an AD converter 2, a memory A31, a memory B32, a display control unit 41, a display unit 5, and a memory control unit 61. The waveform display device of the present embodiment shown in FIG. 1 is configured to digitally convert an analog input signal input to the input amplifier 1 by an AD converter 2 as compared with the configuration of the conventional waveform display device shown in FIG. The waveform display apparatus according to the present embodiment is the same in terms of basic operation for display control of the converted waveform data, but does not include an acquisition memory. Unlike the conventional waveform display device, the memory means and the second memory means are provided with a memory A31 and a memory B32 which are bitmap memories and have the same write capacity.

  Since the memory A31 and the memory B32 are in the bitmap format, the memory control unit 61 uses the digitized waveform data of the input signal as the horizontal and vertical axes of the image on the display screen of the display 5. The memory control unit 61 reads out the written waveform data from the memory A or B immediately after the waveform data is written, outputs the waveform data to the display control unit 41, and outputs the waveform to the display unit 5. indicate. Since such a waveform data writing method is employed, special control processing for displaying the waveform on the display 5 is not required, and the waveform data read from the memory A or B can be displayed sequentially. Since it is good, it becomes unnecessary to provide a display memory in the display control unit 41, and the control can be simplified.

  FIG. 2 is a time chart showing the state of basic control regarding the write operation to the memory A31 and the memory B32 provided in the waveform display device of the present embodiment and the read operation therefrom. 2A shows the frame period, FIG. 2B shows the read or write period of the memory A, and FIG. 2C shows the read or write period of the memory B. Here, the frame period is represented by symbols F1, F2,..., The read period is denoted by an R symbol, and the write period is denoted by a W symbol. The same applies to the time charts described below.

  As shown in FIG. 2a), the memory A corresponds to a frame period F1, F2,... Divided into frames of a certain length corresponding to one image displayed on the display screen of the display 5. Alternatively, the waveform data writing or reading operation of the memory B is performed. In FIG. 2, frame periods F1 to F3 are representatively represented, and each period has the same length, for example, one frame from time t1 to time t2.

  In the frame period F1 from time t1 to time t2, the memory control unit 61 writes the captured waveform data into the memory A, and sequentially stores the waveform data stored in the memory B in a raster form for the memory B. Read and output to the display control device 41. Next, at time t2, in the frame period F2 up to time t3, the memory control unit 61 performs a read operation on the memory A, and sequentially reads the waveform data written in the frame F1 in a raster shape. To the display control unit 41. At this time, a write operation is performed on the memory B to write the acquired waveform data. Even after time t3, such a writing operation and a reading operation are alternately repeated in the memory A and the memory B.

  In this way, the waveform data fetched from the AD converter 2 by the memory control unit 61 is alternately written into the memory A or the memory B for each frame period, so that the waveform data is not missed. In the frame period in which the waveform data writing operation is not performed in the memory B, a read operation for reading the written waveform data is performed. For this reason, display processing can be continuously performed in the acquisition of waveform data, and the dead time that occurs in the conventional waveform display device is eliminated.

  Here, FIG. 3 shows how the waveform data is written into the memory A or the memory B in each frame period. FIG. 3 shows a state in which waveform data for one frame period is written, and the matrix cells schematically represent the memory structure of the memory A or the memory B that is a bitmap memory. The horizontal direction in the figure corresponds to the horizontal axis of the memory bitmap and indicates the memory address, and the vertical direction corresponds to the Y axis of the image on the display screen. Accordingly, the matrix-like cells correspond to the pixels (dots) of the image.

  One image to be displayed on the display screen of the display 5 is generated for each frame, and the waveform data is stored in the bitmap memory each time in response to a plurality of trigger signals generated in the frame. Overwritten and generated. In FIG. 3, this overwriting is expressed as memory write states M1, M2,... In the order of trigger signal generation.

  For example, in the memory write state M1, a state in which waveform data is written in accordance with the first trigger signal in the frame period is shown, and in the memory write state M2, the waveform data is in response to the second trigger signal. The overwritten state is shown. Here, the blank of each cell in each state means that the waveform data is “0”, and the numerical value 1 indicates that the waveform data is “1”. If it is “1” in the memory write state M1 and the same location is “2” in the memory write state M2, the waveform data is overwritten. The brightness at the dot is displayed strongly.

  As shown in FIG. 3, the waveform data is directly written into the memory A or the memory B for each frame, and the waveform data is overwritten and stored for each of a plurality of trigger signals sequentially generated within the frame period. Therefore, the data written in response to the last trigger signal can be used as image data related to the image generated within the frame period, and in the next frame period, the data is read out in a raster form as it is, Thus, the read data can be directly output to the display without performing any display processing, and the display control can be simplified.

  Next, details of the waveform data writing and reading operations for the memories A and B by the memory control unit 61 will be described with reference to the time chart of FIG. 4A shows the frame period, and FIG. 4B shows the generation state of the trigger signal input to the memory control unit 61. C) shows a write gate signal during a write period to the memory A, and d) shows a read or write period of the memory A. Also, e) represents a read or write period of the memory B, and f) represents a write gate signal during the write period for the memory B. And g) represents a trigger enable signal indicating a trigger signal waiting state, that is, a state in which waveform data can be written in the memory A and the memory B.

  Here, in FIG. 4, the frame period of a), the R / W period of the memory A of d) and the R / W period of the memory B of e) are the frame period of a) and the memory A of b) in FIG. This is the same as the R / W period of the memory B and the R / W period of the memory B of c).

  In each frame period, the timing at which the memory control unit 61 writes the waveform data fetched from the AD converter 2 into the memory A or the memory B is determined by the input of the trigger signal to the memory control unit 61. The waveform data corresponding to the memory lengths of the memory A and the memory B is written. From the start of writing until the end of the writing operation for the memory length, the writing operation is prohibited by a trigger signal input after the trigger signal for starting the writing.

  For example, in the frame period F1, the write operation W is performed in the R / W period of the memory A. When the trigger signal is input at the time t1, the memory control unit 61 performs the gate operation of the memory A. A signal is output, waveform data is fetched from the AD converter 2, and writing of the waveform data into the memory A is started. This writing operation is performed until the waveform data for the memory length is completely written, and is finished at time t2. This write operation corresponds to the waveform data write state M1 in FIG. Here, even if the next trigger signal is input before time t2, the write operation for the memory length is in progress, so the write operation is not started by this trigger signal. Therefore, at time t2, the trigger enable signal is set in a trigger signal waiting state.

  Next, at time t3, when a trigger signal is input, the trigger enable signal is set in a trigger signal standby disabled state and a waveform data write operation is started. Then, at time t4, the writing of the waveform data for the memory length is completed, the writing operation is terminated, and the trigger enable signal is set in a trigger signal waiting state. This state corresponds to the waveform data writing state M2 in FIG.

  In the waveform data writing operation after time t4 in the frame period F1, the above-described procedure is repeated, and image data relating to the frame period F1 is generated. With respect to the memory A, at a time t6, the frame A shifts to a frame period F2 following the frame period F1, and a read operation R is performed in the frame period F2. Therefore, the image data generated in the frame period F1 is sequentially read out in a raster shape by the memory control unit 61, sent to the display control unit 41, and displayed on the screen of the display 5.

  On the other hand, with respect to the memory B, the read operation R is performed in the frame period F1, but the write operation W is performed when the frame B is shifted to the frame period F2 at time t6. The write operation to the memory B is performed in the same procedure as the write operation to the memory A. When the trigger enable signal is ready to wait for the trigger signal, for example, when the trigger signal is input at time t7, the memory control unit 61 outputs the gate signal of the memory B and writes to the memory B. Start operation. This writing operation is performed until the waveform data for the memory length is completely written, and is finished at time t8. This write operation corresponds to the waveform data write state M1 in FIG.

  In the waveform data writing operation after time t8 in the frame period F2, the above-described procedure is repeated, and image data relating to the frame period F2 is generated. With respect to the memory B, at a time t13, the frame period F3 follows the frame period F2, and a read operation R is performed in the frame period F3. Therefore, the image data generated in the frame period F2 is sequentially read out in a raster shape by the memory control unit 61, sent to the display control unit 41, and displayed on the screen of the display 5.

  As described above, the write operation W and the read operation R are alternately and sequentially repeated for the memory A and the memory B, so that waveform data is not missed and no dead time is generated. Next, detailed control relating to the above-described write operation W will be described with reference to the time chart of FIG.

  5a shows a clock signal supplied to the AD converter 2, b) shows a part of the trigger enable signal shown in g) of FIG. 4, and c) shows FIG. Part of the trigger signal shown in b) of Fig. 4 is shown, and d) shows the gate signal of c) or f) of Fig. 4. Further, e) shows an address signal output from an address counter provided in the memory control unit 61.

  When the trigger enable signal is in a trigger signal standby state, when the trigger signal is input at time t1, the trigger enable signal changes to the trigger signal standby disabled state, a write gate signal is output, and the address counter Is activated. Therefore, the address counter starts counting from the clock signal at time t2, and continues counting while the write gate signal is output.

  The output period of the write gate signal is set to the memory length, and the address counter sequentially outputs the address values a1, a2, a3,... Each time the clock signal is counted. The address value of this address signal corresponds to the address of the memory as shown in FIG. In the write operation of the waveform data to the memory A or memory B by the memory control unit 61, the waveform data output from the AD converter 2 is synchronized with the clock signal according to the output address signal and corresponds to each dot of the memory. And will be written.

  Next, a detailed operation when the waveform data fetched from the AD converter 2 is written in the memory A and the memory B in accordance with the address signal output as described above will be described with reference to FIG. In FIG. 6, a part is representatively shown. FIG. 6A shows a write clock signal similar to the clock signal of FIG. 5A, and each of the clock signals is displayed. This indicates that one dot of the image corresponds to the first one of the bitmap memory shown in FIG. B) shows the address signal when the write gate signal shown in e) of FIG. 5 is output, and c) is read from the memory at the position corresponding to the address value of the address signal. The read data is shown, and d) shows the write data written in the memory at the position corresponding to the address value of the address signal.

  When the trigger signal is input and the write gate signal is output, the address counter starts counting the write clock signal at time t1. When the address counter outputs the address signal a1, the memory control unit 61 reads the data value d1 stored in the memory corresponding to the output address signal in the first half cycle of the clock signal. Then, in the second half cycle of the clock signal from time t2, the data value dx of one waveform data fetched from the AD converter 2 is added to the read data value d1, and the waveform data of the data value d1 + x is obtained. Data is overwritten by writing.

  In the waveform data writing operation to the memory A and the memory B according to the address signal, reading of stored data and writing of data obtained by adding the data values of the acquired waveform data are repeated for each clock signal. . This continues during the period when the gate signal is output. For example, when the read data value d1 is 0 and the data value of the captured waveform data is 1, the data value to be written is 1. Alternatively, when the read data value d1 is 1 and the data value of the captured waveform data is 1, the data value to be written is 2. In addition, when the data value of the captured waveform data is 0, the data value to be written remains the read data value. As this data value is added, the brightness of the display dot related to this data increases.

  Next, a detailed operation of reading waveform data from the memory A and the memory B by the memory control unit 61 will be described with reference to FIG. In FIG. 7, a part is representatively shown, and a) in FIG. 7 shows a read clock signal similar to the clock signal in a) in FIG. 5, and each of the clock signals is displayed. It corresponds to one dot of the image, that is, the first one of the bitmap memory shown in FIG. B) shows an address signal output during the read operation R shown in d) and e) of FIG. 5, and c) reads from the memory at the position corresponding to the address value of the address signal. And d) shows the write data to be written in the memory at the position corresponding to the address value of the address signal. The same e) shows read output data read from the memory A and the memory B according to the address signal and output to the display control unit 4.

  As shown in FIG. 5 d) and e), when the frame period of the write operation is shifted to the frame period of the read operation, the raster address counter for reading sequentially starts to count the read clock signal at time t1. . When the raster address counter outputs the address signal b1, the memory control unit 61 reads the data value d1 stored in the memory corresponding to the output address signal in the first half cycle of the read clock signal. Then, in the latter half cycle of the clock signal, the read data value d1 is output to the display control unit 41 as read output data. Similarly, in the read clock signal at the next time t3, when the raster address counter outputs the address signal b2, the data value d2 is read and output.

  On the other hand, when it is desired to perform the afterglow processing of the waveform in the display image on the display device 5, as shown in d) of FIG. 7, the predetermined data value dx is subtracted from the data value read out in c). Data is overwritten by writing waveform data of value d1-x. When the afterglow processing of the waveform is not performed, the write operation by the write data shown in d) of FIG. 7 can be prevented, or the predetermined data value dx to be subtracted can be set to zero.

  As described above, according to the waveform display device of the present embodiment, digitized waveform data is directly and alternately written directly into the memory A and the memory B in the bitmap format. By sequentially reading the waveform data in a raster pattern, the read data is displayed as display data as it is, eliminating the need to use an acquisition memory, and eliminating the need for display memory in the control means. Thus, it is possible to simplify the control relating to the waveform data writing and reading operations and the control for waveform display.

  Then, the waveform data is directly written on the memory in the form of a waveform display image, and the next trigger signal can be waited immediately after the waveform data is written without waiting for control processing by software for waveform display. Therefore, the waveform display can be updated at high speed, and the display state on the analog oscilloscope can be brought close to. Further, since the waveform data writing operation and the reading operation can be executed alternately in the memory A and the memory B without any break, real-time display can be realized without causing any dead time.

  Next, a second embodiment of the waveform display device of the present invention will be described with reference to FIGS. FIG. 8 is a block diagram illustrating a schematic configuration of the waveform display device according to the second embodiment. Unlike the waveform display device of the first embodiment shown in FIG. 1, the waveform display device of this embodiment includes input amplifiers 11 and 12 that receive an input signal S (x) and an input signal S (y), and The AD converters 21 and 22 digitize these input signals. The second embodiment is the same as the first embodiment in that the memory A31, the memory B32, the display control unit 42, the display 5, and the memory control unit 62 are provided.

  In the waveform display device of the second embodiment, the memory A31 and the memory B32 employ the bit map memory as in the first embodiment, but the memory control unit 62 is digitized. The data based on the input signals S (x) and S (y) are stored in the bitmap memory in correspondence with the horizontal axis (X axis) and vertical axis (Y axis) coordinates of the image on the display screen of the display 5. I try to write. The memory control unit 62 reads out the written waveform data from the memory A or B and outputs it to the display control unit 41 immediately after the data related to the input signals S (x) and S (y) is written for each frame period. The waveform is displayed on the display 5.

  The basic control regarding the write operation to the memory A31 and the memory B32 and the read operation from the memory A31 and the memory B32 provided in the waveform display device of the present embodiment is the time chart shown in FIG. 2 as in the case of the first embodiment. Is executed. As shown in FIG. 2a), the memory A corresponds to a frame period F1, F2,... Divided into frames of a certain length corresponding to one image displayed on the display screen of the display 5. Alternatively, the waveform data writing or reading operation of the memory B is performed.

  Next, details of the write operation and the read operation of the input signal data to the memory A and the memory B by the memory control unit 62 will be described with reference to the time chart of FIG. 9a shows the frame period, and FIG. 9b shows the write enable signal to the memory, as in FIG. C) shows a write gate signal during a write period to the memory A, and d) shows an R / W period of the memory A. Also, e) represents the R / W period of the memory B, and f) represents the write gate signal during the write period for the memory B.

  9, the frame period of a), the R / W period of the memory A of d), and the R / W period of the memory B of e) are the frame period of a) and the memory A of b) in FIG. This is the same as the R / W period of the memory B and the R / W period of the memory B of c).

  In each frame period, the timing at which the memory control unit 62 writes the digital data related to the input signal fetched from the AD converter 2 into the memory A or B is different from that in the first embodiment. It is output to “H” so that it can be written at any time. When the memory control unit 62 shifts from the frame period of the read operation of the memory A or the memory B to the frame period of the write operation, the memory control unit 62 starts writing the digital data into the memory A or the memory B, The data for one image of the display screen in the device 5 is written. As in the case of the first embodiment, since the write start is not based on the trigger signal, the write enable signal is always output to the high level “H”.

  For example, in the frame period F1, the write operation W is performed in the R / W period of the memory A, and the memory control unit 62 starts the write operation W at the time t1 to the memory A. , Based on the digital data of the captured input signal S (x), corresponding to the X-axis coordinates in the image of the display screen, and based on the digital data of the captured input signal S (y), the Y-axis coordinates of the image For example, data having a data value of 1 is written in a storage location specified on the bitmap memory. This writing operation is performed until the frame period is switched, and ends at time t2, and image data for one image is stored in the memory A.

  Next, at the time t2, when the frame period F1 is switched to the frame period F2 and shifted, the R / W period shifts from the write operation period to the data read period with respect to the memory A. A read operation R is performed on A. Therefore, the image data generated in the frame period F1 is sequentially read out from the memory A in a raster shape by the memory control unit 61, sent to the display control unit 41, and displayed on the screen of the display 5.

  On the other hand, for the memory B, the read operation R is performed in the frame period F1, but the write operation W is performed when the frame B is shifted to the frame period F2 at time t2. The write operation to the memory B is performed in the same procedure as the write operation to the memory A. The memory B is associated with the X-axis coordinate in the image of the display screen based on the digital data of the input signal S (x) acquired, and the digital data of the input signal S (y) acquired. In association with the Y-axis coordinates of the image, for example, data having a data value of 1 is written in a storage location specified on the bitmap memory. This writing operation is performed at time t3 until the frame period F2 is switched to the frame period F3, and image data for one image is stored in the memory B.

  When the image data related to the frame period F2 is generated, the memory B shifts to a frame period F3 following the frame period F2 at time t3, and a read operation R is performed in the frame period F3. Therefore, the image data generated in the frame period F2 is sequentially read out in a raster shape by the memory control unit 61, sent to the display control unit 41, and displayed on the screen of the display 5.

  As described above, in the waveform display device according to the second embodiment, the input signal S (x) is input as the first input signal, the input signal S (y) is input as the second input signal, and each input signal is input. Digitize to generate two digital data, one digital data as the coordinate value of the horizontal axis of the display image, and the other digital data as the coordinate value of the vertical axis, corresponding to the dot of the image for image display The image data is alternately written in the memory A or the memory B, and when the write operation is performed on one of the memories, the read operation is performed on the other memory. The trigger signal becomes unnecessary. In addition, since the waveform display image is directly written into the memory, the control for writing and reading the waveform display data and the control for displaying the waveform can be simplified. Moreover, the waveform display is not interrupted by the memory length, and gradation display can be realized.

  In the waveform display device of the first embodiment described above, the write enable signal always maintains the writable state. However, if the writable state is always maintained, the waveform displayed on the display screen may be partially biased to the screen or may be dense. When such a waveform display state is obtained, the waveform portion becomes planar and the luminance increases, and as a result, the displayed waveform becomes unclear or the waveform is crushed.

  Therefore, as a measure for avoiding such a waveform display state, the number of data is reduced, and the write enable signal is not always in a writable state, but the writable state of the write enable signal is partially limited. I did it. FIG. 10 shows a time chart of a write operation or a read operation when the writable state is partially limited.

  In FIG. 10, as in the time chart of FIG. 9, a) in FIG. 10 shows a frame period, and b) shows a write enable signal to the memory. C) shows a writing period during a writing period to the memory A, and d) shows an R / W period of the memory A. Also, e) represents the R / W period of the memory B, and f) represents the write period during the write period to the memory B.

  The time chart of FIG. 10 differs from the time chart of FIG. 9 in that the write enable signal b) is, for example, from time t1 to time t2 in the frame period F1, and from time t3 to time t4 in the frame period F2. Thus, the period of the writable state is partially limited. As shown in FIG. 10B), the number of data written to the memory A or the memory B is also limited even if the frame period is the writing period W for the memory A or the memory B by limiting the writing period. And less than the digital data captured over the entire frame period.

  For this reason, even if the waveform displayed on the display screen is partially biased or concentrated on the screen, if the waveform display state is limited, the waveform portion becomes planar and the luminance decreases. As a result, the displayed waveform becomes clear without being crushed. In FIG. 10, the length of the writable period of the write enable signal is the same in each frame period, but the length of the writable period may be changed to an arbitrary size by the user. Further, the length may be changed for each frame period.

  Next, a configuration according to a modification of the waveform display device of the second embodiment is shown in a block diagram in FIG. The configuration of the waveform display device according to this modification is based on the waveform display device shown in FIG. 8, but the input signal is not limited to the input signal S (x) and the input signal S (y). S (z) is input. By inputting the input signal S (z), external luminance modulation can be performed on image data generated based on the input signal S (x) and the input signal (y).

  As shown in FIG. 11, the waveform display device according to the modification of the second embodiment includes input amplifiers 11 to 13 that receive an input signal S (x), an input signal S (y), and an input signal S (z). And AD converters 21 to 23 for digitizing these input signals. The second embodiment is the same as the second embodiment in that the memory A31, the memory B32, the display control unit 43, the display 5, and the memory control unit 63 are provided.

  In the waveform display device according to the modification of the second embodiment, the write operation and the read operation for the memory A and the memory B are alternately performed for each frame period based on the input signal S (x) and the input signal S (y). As a result, the image data to be displayed on the display screen of the display 5 can be generated, and the processing procedure is the same as in the time charts of FIGS.

  When the memory control unit 63 generates data corresponding to one dot based on the digital data of the input signal S (x) and the input signal S (y) in the writable period for the memory A or the memory B, The data value is weighted with the data value of the digital data of the input signal S (z). By this processing, the image data generated in the frame period is subjected to luminance modulation by the input signal S (z), and external luminance modulation in the waveform display device is realized.

It is a block diagram explaining the structure of 1st Embodiment which concerns on the waveform display apparatus of this invention. It is a time chart figure explaining the basic operation of the writing to the memory concerning the waveform data adopted in the waveform display device of this embodiment, and reading. FIG. 3 is a schematic diagram of a memory for explaining how waveform data is written to a bitmap memory within one frame period. It is a time chart explaining the detailed operation | movement of writing to the memory regarding the waveform data for every frame period, and reading. It is a time chart explaining operation | movement of the address counter at the time of writing to the memory of waveform data. It is a time chart figure explaining the write-in operation to the memory of waveform data. It is a time chart explaining the read-out operation from the memory of waveform data. It is a block diagram explaining the structure of 2nd Embodiment which concerns on the waveform display apparatus of this invention. It is a time chart explaining the detailed operation | movement of writing to the memory regarding the waveform data at the time of enabling writing in all the frame periods, and reading. It is a time chart explaining the detailed operation | movement of writing to the memory regarding the data when the writing period in each frame period is restrict | limited, and reading. It is a block diagram explaining the structure by the modification of 2nd Embodiment which concerns on the waveform display apparatus of this invention. It is a block diagram explaining the structure which concerns on the waveform display apparatus by a prior art. It is a figure explaining the write-in operation | movement of the waveform data to an acquisition memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 11-13 Input amplifier 2, 21-23 AD (analog-digital) converter 3 Acquisition memory 31 Memory A
32 memory B
4, 41-43 Display control unit 5 Display unit 6, 61-63 Memory control unit 7 CPU (Central processing unit)

Claims (9)

Waveform data generating means for generating waveform data by digitizing an input signal;
A display for displaying an image of a signal waveform based on the generated waveform data;
First and second storage means in bitmap format capable of storing the waveform data for each frame period;
For each of the first and second storage means, the waveform data write operation and the waveform data read operation of the written frame period are alternately repeated for each frame period, The waveform data for each frame period is written in one storage means or the second storage means in association with the horizontal axis and the vertical axis of the bitmap relating to the image display, and the first storage means and the second storage means Control means for sequentially reading out the waveform data of the frame period from the output, outputting the read waveform data to the display, and displaying the signal waveform as an image;
A waveform display device.   When the waveform data is alternately written into the first storage unit and the second storage unit for each frame period, the control unit is configured to display the image according to a trigger signal generated during the frame period. 2. The waveform display apparatus according to claim 1, wherein the waveform data corresponding to one image is written in the first storage means or the second storage means.   The control means overwrites the waveform data corresponding to one image of the image display in the first and second storage means for each of a plurality of trigger signals generated during the frame period. 2. The waveform display device according to 2.   When the waveform data corresponding to one image of the image display is overwritten in the first and second storage units, the control unit applies the dot in the image written in the first and second storage units. 4. The waveform display device according to claim 3, wherein the corresponding waveform data value is read, and the waveform data value overwritten on the waveform data is added and written as waveform data corresponding to the dot.   When the waveform data corresponding to one image of the image display is overwritten in the first and second storage units, the control unit applies the dot in the image written in the first and second storage units. 4. The waveform display device according to claim 3, wherein the corresponding waveform data value is read out, and a predetermined value is subtracted from the waveform data value and written as waveform data corresponding to the dot. The waveform data generation means generates first and second data by digitizing the first and second input signals, respectively.
The control means uses the first data as the coordinate value of the horizontal axis, the second data as the coordinate value of the vertical axis, and the waveform data associated with the dots of the image related to the image display as the first data. The waveform display device according to claim 1, wherein the waveform display device writes the data into the second storage means.   The said control means restrict | limits the writable period of the said waveform data to the said 1st and 2nd memory | storage means for every said frame period according to the display state of the said signal waveform. Waveform display device.   The waveform display apparatus according to claim 7, wherein the control unit can change a length of the writable period for each frame. The waveform data generating means digitizes a third input signal to generate third data,
9. The waveform display device according to claim 6, wherein the control unit performs luminance modulation by changing an addition value based on the third data for each waveform data. 10.

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