JP2002156388A - Digital oscilloscope and memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital oscilloscope with a high waveform updating rate by processing raster conversion at a high speed using a simple configuration. SOLUTION: This digital oscilloscope is provided with an analog-to-digital converting means for converting an input analog signal into quantized time series data, a memory means composed so that an address value M of a first port to be converted into bit map format data from the time series data and data written from an N-th bit of a data array are read from an address value N of a second port and an M-th bit of the data array, and a data-converting means for outputting bit map data read from the memory means as display data. The display data can be produced merely by writing the waveform data into a memory circuit and then reading it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital oscilloscope and a memory circuit, and more particularly to a digital oscilloscope and a memory circuit capable of writing display data after writing captured waveform data to a memory and then reading the data. .

[0002]

2. Description of the Related Art A general digital oscilloscope is:
First, the analog signal is analog-digital (A / D)
The data is quantized by the conversion circuit and temporarily stored in the capture memory as time-series data. Next, the data is converted into a bitmap format, stored in a display memory, and then displayed on a raster scanning type display device.

[0003] In a commonly used display format, a time-series data value is indicated on a Y-axis, and the time is indicated on an X-axis.
For example, if the value of the time series data is “4, 5, 5, 6, 6, 6, 6, 5, 5, 4, 3, 2,
In the case of "2, 1, 1, 1", the display screen of the display device is as shown in FIG. 8, the horizontal axis represents the X axis, the vertical axis represents the Y axis,
The input voltage level of the fetched waveform data is indicated by a cross.

At present, a liquid crystal display (LCD) scanning method often used for display of a digital oscilloscope is, for example, scanning from the upper left pixel to the right (the highest row), and then scanning below the upper left pixel. The rows are scanned in order, and finally the bottom row is scanned, and one screen is completed with the bottom right pixel. The contents of the display memory are
Since it is efficient to configure the reading order so as to match the output order to the LCD, when the word configuration of the display memory is 8 bits, the time-series data shown in FIG.
Convert to bitmap format as shown in (rasterization)
There is a need to.

Thereafter, the display memory is read out in ascending order of address, and is output to the LCD in order from the LSB of each word, thereby obtaining a display as shown in FIG. Among them, rasterization includes the following processing. (1) “0” is written to all of the waveform display area of the display memory and initialized. (2) The address value and the bit position on the display memory are calculated from the time series data value and the time. (3) Read out all the 8-bit data at the above address,
Store in buffer. (4) Only one bit in the buffer corresponding to the bit position,
Overwrite "1". (5) Write the contents of the buffer back to the above address. (6) The processes from (2) to (5) are sequentially repeated by the number of data.

In a conventional digital oscilloscope, an inexpensive one-port SRAM is generally used to perform such processing, but a two-port SRAM may be used for the purpose of speeding up the processing. FIG. 12 shows a one-port SRAM cell constituting these memories, and FIG. 10 shows a two-port SRAM cell. These SRAM cells hold data in a pair of storage nodes n1 and n2 by coupling inputs and outputs of a pair of inverter circuits IN1 and IN2.

In the case of a one-port SRAM cell, data transfer circuits MA1 and MA2 selected by a word line WL are connected to a pair of storage nodes n1 and n2.
A complementary pair of bit lines BL1 and NBL1 are connected to input / output data. In the case of a two-port SRAM cell, a pair of storage nodes n1 and n2 are connected to a two-port word line W.
Data transfer circuit MA selected by L1 and WL2
1, MA2 and MA3, MA4 are connected, and a complementary pair of bit lines BL1 and NBL1, and a complementary pair BL2 and NBL
2 to input and output data.

FIG. 11 shows the structure of a general memory cell array constituting the above-described two-port SRAM cell array. Array of word lines of the first port (..., WL1 _m , WL1 _{m + 1} ,
…) And the word line arrangement of the second port (…, WL2 _m ,
WL2 _{m + 1} ,...) Are the same. Similarly, the arrangement of the bit lines of the first port (..., BL1 _m , NBL1 _m , BL
_{1 m + 1, NBL1 m +} 1, ...) and the sequence of the second port of the bit lines _{(..., BL2 m, NBL2 m} , BL2 m + 1, NBL2
_{m + 1} ,...) are the same, and in such a configuration, data written from the first port is directly read from the second port.

From the structure of such a memory cell array,
The above-described processing for converting the quantized data into the bitmap format has been performed.

[0010]

However, in a digital oscilloscope, when converting quantized data into a bitmap format, a 2-port S shown in FIG.
When the RAM cell or the one-port SRAM cell shown in FIG. 12 is used, the above-described complicated processing (1) to (6) must be performed.

Therefore, a digital oscilloscope having a high waveform update speed has a problem that a high-speed CPU and complicated hardware must be provided in order to speed up the rasterizing operation. An object of the present invention is to provide a digital oscilloscope having a simple configuration and high-speed processing of a rasterizing operation, and having a high waveform update speed.

[0012]

In order to solve the above problems, the present invention provides a digital oscilloscope comprising:
Analog-digital conversion means for converting an input analog signal into quantized time-series data, memory means for sequentially writing the time-series data and reading data converted to a bitmap format, and read-out data from the memory means Data conversion means for outputting the bitmap format data as display data, and display means for displaying the display data. The memory means reads the address value M at the first port and the data written from the Nth bit of the data array from the address value N at the second port and the Mth bit of the data array. Time-series data is converted to bitmap data and output.

According to the present invention, in a digital oscilloscope, a first memory means for storing waveform data and a second memory for sequentially ORing and synthesizing waveform data read from the first memory means are provided. Means, and display means for displaying the synthesized waveform data read from the second memory means. After the plurality of waveform data are temporarily stored in the memory, the read waveform data is synthesized and displayed. As described above, the second memory means is a waveform synthesizing conversion means for synthesizing and displaying a plurality of image data, and only by writing data to the memory,
Data obtained by performing an OR operation on data immediately before writing to the memory cell and data written to the memory cell is stored in the memory cell.

Further, according to the present invention, in a digital oscilloscope, analog-digital conversion means for converting an input analog signal having a plurality of waveforms into a plurality of quantized time-series data, and first memory means for storing the time-series data A second memory for sequentially ORing the time-series data read from the first memory and converting the data into a single bitmap format; and a second memory for reading the data from the second memory. Data conversion means for outputting the obtained bitmap data as display data, and display means for displaying the display data, wherein the second memory means has first and second ports, and has a plurality of waveforms. By writing the time-series data from the first port, a logical sum is synthesized in a bitmap format, and the output format of the waveform display is output from the second port. It was to read to.

According to the present invention, in a memory circuit in which time-series data of an input signal can be written and from which the written data can be read, the address value M at the first port and the N-th bit of the data array are determined. The written data is read from the address value N at the second port and the M-th bit of the data array, and the time-series data is converted into bitmap data and output.

Furthermore, according to the present invention, in a memory circuit for performing waveform synthesis conversion for synthesizing and displaying a plurality of image data, only the operation of writing data to the memory is performed.
Data obtained by performing an OR operation on data immediately before writing to the memory cell and data written to the memory cell is stored in the memory cell.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described.
This will be described with reference to FIGS. FIG. 1 shows the structure of a two-port memory cell array showing the first feature of the present embodiment. As shown in FIG. 1, as compared with the conventional two-port memory cell array shown in FIG. 11, the arrangement of the first ports and the arrangement of the second ports are replaced by word lines and bit lines.

By adopting such an arrangement, for example, the memory cell (m) accessed by the complementary pair BL1 _n , NBL1 _n of the m-th word line WL1 _m and the n-th bit line for the first port. , N) 22 will be accessed by the n-th word line WL2 _n for the second port and the complementary pair BL2 _m , NBL2 _m of the m-th bit line.

As a result, the data written from the first port is read out from the second port, thereby having a function of converting the data into a bitmap format. FIG. 2 is a configuration diagram of a two-port memory circuit having the memory cell array shown in FIG. The time-series data from the analog-to-digital conversion circuit relating to the fetched waveform data is usually 8-bit encoded data.
Using the decoding circuit, the decoded 256-bit data is input to the data input buffer 6 as the data DAT1 of the first port of the memory circuit. The data DAT2 of the second port is sent from the data output buffer 7 to
The data is output to a parallel-serial (P / S) conversion circuit which sequentially outputs the data to the LCD as one line of bitmap data.

In the operation mode of the LCD, the memory cell array is configured such that the number of pixels in the Y direction of the display screen is a bit configuration of the first port, and the number of pixels of the display screen in the X direction is a bit configuration of the second port. It is desirable that they match. Of course, the region where the waveform is not displayed may be omitted. In the description so far, an example of the static method has been shown as the memory means of the memory circuit. However, other means such as a dynamic method may be used.

Next, regarding these operations, here,
For the sake of simplicity, the configuration of the memory cell array is assumed to be 8 cells in the Y direction and 16 cells in the X direction, and an example will be described with reference to the waveform shown in FIG. One cell corresponds to one pixel of the LCD. The time series data described in FIG. 8 is written via the input buffer 6 of the first port of the memory circuit. By writing the address at this time while incrementing the address from “0000”, the time series data fetched and quantized is written into the memory cell array in a manner as shown in FIG. 3 corresponding to each memory cell. It is.

It can be easily understood that the contents shown in FIG. 3 are the same as the images on the display screen in FIG. 8, and "1" in the figure indicates data corresponding to the input level of the waveform to be displayed. It indicates that there is. Next, based on these written data, each data is read through the data output buffer 7 of the second port in the memory circuit in order to display the captured waveform.

At this time, as shown in FIG. 3, the addresses of the first port and the second port are designated and the address "1" is set.
Each data is read out while being decremented from 111 ", and further, the read out data is sequentially output to the LCD from the LSB side via a conversion means such as a parallel-serial conversion circuit. It is possible to easily convert the data in the format into the data in the display format, and in this conversion, complicated control means and circuits as in the related art are not required, and high-speed rasterization processing is possible.

Needless to say, the arrangement direction of the LCD and other LCDs
And other display devices, there are various output orders of display data. However, the same operation can be performed only by changing the operation of the address. In the memory circuit according to the present embodiment, it is the simplest configuration to configure all pixel arrays of the display screen with a single memory circuit. However, a plurality of small memory circuits (hereinafter, referred to as small memory circuits, Is also possible.

For example, FIG. 4 shows a case where the length and width of a single memory circuit are equally divided and divided into a total of four small memory circuits.
Shown in In FIG. 4, small memory circuits are denoted by reference numerals 10 to 13. In FIG. 4, the addresses except the MSB of the entire first port are connected to the addresses of the first ports from the small memory circuit 10 to the small memory circuit 13, respectively. The selection of the first ports of the circuits 1 and 2 and the first ports of the small memory circuits 3 and 4 is made.

The data of the entire first port is higher (MS)
Half of the bits (on the B side) are connected as the data of the first port of the small memory circuits 1 and 3, and the lower (LSB side) half of the bits are connected as the data of the first port of the small memory circuits 2 and 4. . FIG. 4 shows only the connection of the first port, but the second port is omitted for the sake of simplicity in the description, and the second port can be realized by the same connection method.

Further, it can be understood that the time range change in the display waveform, the simultaneous display of a plurality of channels, and the movement of the waveform, which are functions required for the oscilloscope, can be easily performed. For example, when writing from the first port of the memory circuit, the X direction of the display waveform can be enlarged by changing the increment value of the memory address. In addition, by performing enable control of the write operation from the first port, decimation of time-series data is performed,
It is also possible to compress the display waveform in the X direction.

Further, by performing a logical sum of data to be written from the first port in each display channel, it is possible to display a plurality of channels. Furthermore, when data is read from the second port and output from the parallel-serial (P / S) conversion circuit, the trigger point can be moved or the screen can be scrolled by changing the data output order. it can.

As described above, the capture memory, the rasterizing circuit, and the display memory required by the conventional oscilloscope can be replaced with the memory circuit according to the present embodiment. As shown in FIG. 5, a digital oscilloscope is constituted by the analog-digital conversion circuit 14, the decoding circuit 15, the memory circuit 16, the parallel-serial conversion circuit 17, and the display device 18.
The memory circuit of FIG. 2 according to the present embodiment is used. The control unit 19 controls the read address of the memory circuit 16 and displays each data read sequentially on the display device 18.

As described above, by using the memory circuit according to the present embodiment, a digital oscilloscope can be realized with a simple configuration. Thereby, downsizing and cost reduction of the digital oscilloscope can be achieved at the same time. next,
Instead of the conventional one-port SRAM cell shown in FIG.
FIG. 6 shows an example of a one-port SRAM cell having the second feature of the present invention.

This memory cell is different from the general one-port SRAM cell shown in FIG. 12 in that one side IN1 of a pair of inverter circuits constituting a data holding circuit is replaced with a NAND circuit NAND1. Data transfer circuit M
A1, MA2 and write control circuits MAC1, MA in series
C2 is connected to the output node n of the inverter circuit IN2.
1 and a write signal WR are controlled by a NAND circuit NAND2.

Further, the contents of the memory cell are erased ("0").
2), one input terminal NERS of the NAND circuit NAND1 is added. In the write operation (WR = “H”) once after the node n1 once becomes “H”, the data holding circuit including the nodes n1 and n2 is separated from the others by the write control circuits MAC1 and MAC2. , SRAM cell data is retained.

Of course, the one-port SRAM cell can be changed to various other circuit configurations. The overall configuration of the memory circuit can be realized in the same manner as the configuration of a general SRAM, and thus the description is omitted. Next, FIG. 6 illustrates this operation.

In the initial state, when the input terminal NERS goes to "L", all the nodes n1 of each memory cell are initialized to "L". Then, after "H" is input to the input terminal NERS, the first data is written. This case is the same as a normal write operation. Next, the second data is written, and the waveform data is synthesized.

In this operation, the first data is "L" (n1
If the first data is "H" (the node n1 is "H"), the second data is written. Since the contents are retained, the second data is not written. As described above, once "H" is written in the SRAM cell, the cell data is retained thereafter, thereby implementing the OR operation in the memory cell.

By writing the waveform data several times and then reading the data, synthesized data of the waveform can be easily obtained. Thereafter, by inputting "L" to the input terminal NERS, all of these waveform data are instantaneously erased and new waveform data can be written. FIG. 7 shows an example of a memory cell having both the first and second features of the present invention.

In FIG. 7, the data transfer circuit MA1 on the port 1 side is determined by the value of the node n2 of the data holding circuit composed of the NAND circuit NAND1 and the inverter circuit IN2.
And MA2, it is possible to perform OR writing. The configuration of the cell array and the memory circuit is shown in FIG.
And FIG. The two-port memory circuit composed of these writes the first time-series data and then writes the second, third, etc. time-series data, and superimposes them as a single bitmap format data. The combined display data can be read from the second port.

The digital oscilloscope provided with this memory circuit can achieve a high waveform update speed. Further, by providing a plurality of the present memory circuits, one of which is operated for writing time-series data and the other is operated for reading display data, and alternately utilizing these, a higher waveform update speed can be obtained. .

[0039]

As described above, according to the present invention, in the digital oscilloscope, the arrangement of the first port and the arrangement of the second port are replaced by the word lines and the bit lines, thereby providing the waveform data. Since the display data can be created simply by writing the data to the memory circuit and then reading it out, a high-speed waveform update speed is possible, and the configuration of the digital oscilloscope can be simplified without requiring a complicated conversion circuit. The price can be reduced.

[Brief description of the drawings]

FIG. 1 shows a two-port SRAM having a first feature of the present invention.
3 is a configuration diagram of the memory cell array of FIG.

FIG. 2 is a configuration diagram of a memory circuit having a first feature of the present invention.

FIG. 3 is a diagram for explaining a write operation and a read operation according to the first feature of the present invention;

FIG. 4 is a diagram for explaining a modified example of the memory circuit of the present invention.

FIG. 5 is a diagram showing a configuration example of a digital oscilloscope according to the present invention.

FIG. 6 shows a one-port SRAM having the second feature of the present invention.
It is a figure showing the example of composition of a cell.

FIG. 7 is a diagram showing a configuration example of a two-port SRAM cell having the first and second features of the present invention.

FIG. 8 is a diagram illustrating an example of a display screen of the waveform display device.

FIG. 9 is a diagram for explaining a bitmap memory;

FIG. 10 is a configuration diagram of a general two-port SRAM cell.

FIG. 11 is a configuration diagram of a memory cell array of a general two-port SRAM.

FIG. 12 is a configuration diagram of a general one-port SRAM cell.

[Explanation of symbols]

 1 to 4, 20 to 23 Memory cell 5 Memory cell array 6 Data input buffer 7 Data output buffer 8 First port word line decoder 9 Second port word line decoder 10 to 13 Small memory circuit 14 Analog -Digital conversion circuit 15 ... Decoding circuit 16 ... Memory circuit 17 ... Parallel-serial conversion circuit 18 ... Display device 19 ... Control means

Claims (8)

[Claims] An analog-to-digital converter for converting an input analog signal into quantized time-series data; a memory for sequentially writing the time-series data and reading data converted to a bitmap format; A digital oscilloscope comprising: data conversion means for outputting bitmap format data read by the means as display data; and display means for displaying the display data. 2. The memory means includes a first port and a second port, and an address value M at the first port and data written from an Nth bit of a data array are stored in the first port.
Reading from the address value N and the Mth bit of the data array at the second port,
2. The method according to claim 1, wherein the data is converted into bitmap data and output.
2. A digital oscilloscope according to claim 1. 3. A digital oscilloscope for temporarily storing a plurality of digitized waveform data in a memory, and then combining and displaying the read waveform data, wherein the first memory means stores the waveform data. A second memory for sequentially ORing and synthesizing the waveform data read from the first memory; and a display for displaying the synthesized waveform data read from the second memory. A digital oscilloscope comprising: 4. The second memory means is a waveform synthesizing and converting means for synthesizing and displaying a plurality of image data. 4. The digital oscilloscope according to claim 3, wherein data obtained by performing an OR operation on data written to the memory cell is stored in the memory cell. 5. An analog-to-digital converter for converting an input analog signal having a plurality of waveforms into a plurality of quantized time-series data, a first memory for storing the time-series data, and the first memory. A second memory means for sequentially ORing the time-series data read from the memory and converting the time-series data into a single bitmap data; and the bitmap data read from the second memory means. A digital oscilloscope comprising: data conversion means for outputting the data as display data; and display means for displaying the display data. 6. The second memory means has first and second ports, and writes time series data of a plurality of waveforms from the first port to perform a logical sum synthesis in a bitmap format. 6. The digital oscilloscope according to claim 5, wherein the digital oscilloscope reads data from the second port in the order of the output format of the waveform display. 7. A memory circuit to which time-series data of an input signal can be written and from which the written data can be read, wherein an address value M at a first port and a data array N
The data written from the second bit is read from the address value N at the second port and the Mth bit of the data array, and the time series data is converted into bitmap data and output. Memory circuit. 8. A memory circuit for performing waveform synthesis conversion for synthesizing and displaying a plurality of image data, the data being written into a memory, the data immediately before writing into the memory cell and the data being written into the memory cell. A memory circuit which stores data obtained by performing a logical OR operation on the memory cell, reads out the stored data, converts the data into bitmap data, and outputs the data.