JPH05196646A - Waveform display storing circuit - Google Patents

Abstract

PURPOSE:To provide a waveform display storing circuit in which brightness of the entire screen does not change even when a time base is changed, when waveforms are stored to be displayed. CONSTITUTION:A waveform display storing circuit comprises image memory 8, an initial period data formation circuit, a change value setting means 2 for inputting the data from the image memory 8 and for outputting a data signal to a selection means 6, a writing address formation circuit 4 for forming an address at the time of writing the data in the image memory 8 by external control, a display address formation means 5 for forming the address at the time of reading the data for display from the image memory 8, and a pseudo random number formation means 3 for forming an address for changing the data of the image memory 8. Further, a data conversion means 9 for inputting the data for display from the image memory 8 and for converting it into a signal corresponding to the data at the time of displaying, and a display brightness control circuit 10 for outputting a signal for changing the brightness of the image memory 8, are also provided. When waveforms which are collected in different time period are to be stored and displayed, stages of gradient of the brightness due to the time difference are smooth even when a change occurs in the time base.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform display storage circuit which, when storing and displaying waveforms having different acquisition times, displays the time difference as a change in luminance gradation.

[0002]

2. Description of the Related Art First, the concept of a method of accumulating the time change of a waveform and displaying the time change by a change in luminance will be described. In this case, the data stored at each address of the image memory having the structure shown in FIG. 2 becomes the data of each pixel, and this data becomes the time information, that is, the information indicating the gradation of luminance.
The pixel means a minimum unit of display of a display means, especially a digital CRT, and is as shown in FIG. Therefore,
In displaying such a waveform, as shown in FIG. 2, refresh memories 81 to 8 m are provided for each bit of the image memory.
Think of as a memory space. This data is read and the brightness is determined according to the data.

The conventional so-called accumulated display for superposing and displaying waveforms captured at a plurality of times is as follows. At each address of the image memory corresponding to the pixel, information on whether to display the pixel and information on the written time are simultaneously written, and at the time of display, the difference between the written time and the read time, It represented the change in brightness gradation. This technique is described in detail in JP-A-1-318966 by the present applicant. In such a configuration, when the information of the present time suddenly changes due to the passage of time, the difference between the written time and the read time suddenly changes, and thus the brightness suddenly changes.

[0004]

For this reason, there is a problem in that the luminance of the entire screen changes when the time change of the waveform is accumulated and displayed, which gives an unnatural impression to the observer of the display screen. there were. Therefore, an object of the present invention is to realize a circuit in which the luminance of the entire screen does not change rapidly with the passage of time when waveforms are accumulated and displayed.

[0005]

According to the present invention, there is provided an image memory in which data of a plurality of display pixels arranged two-dimensionally is stored, and a selection means for selecting a data signal to be input to the image memory. An initial time data generation circuit for inputting a data signal to the selecting means, a change value setting means for inputting data from the image memory and inputting a data signal to the selecting means, and an image memory A write address generation circuit that generates an address when writing data by external control, an article random number generation unit that generates an address when reading data for display from the image memory, and data in the image memory From the write address generating circuit, the display address generating means, and the pseudo random number generating means. Switching means for switching signals to output to the image memory, data conversion means for inputting data for display from the image memory and converting to signals corresponding to data at the time of display, and displaying signals from the conversion means A display brightness control circuit for outputting as a signal capable of changing the brightness and display means for displaying based on the signal from the display brightness control circuit are provided, and waveforms with different acquisition times are accumulated and displayed. In this case, the waveform display storage circuit is characterized in that the gradation level of the brightness due to the time difference is smooth.

[0006]

[Function] The data to be written in the image memory is always displayed at the maximum brightness when the first writing is performed,
The data is rewritten in accordance with the conditions so that the gradation of the luminance changes gradually, so that the gradation of the luminance of the entire screen does not change abruptly with the change of time.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.
FIG. 1 is a basic configuration diagram of the present invention. In FIG. 1, 1
Is an initial time data generation circuit, and this output data signal is input to the data terminal of the image memory 8 via the switching means 7. Reference numeral 2 is a change value setting means, which comprises a register 21 and a time data change circuit 22. The register 21 holds the output data signal from the time data changing circuit 22 as temporary data and inputs it to the data terminal from the image memory 8 via the selecting means 6. The time data changing circuit 22 inputs the data of the address designated by the pseudo random number generating means 3 from the image memory 8 and increments the value thereof to register 21.
Output to. The time data changing circuit 22 is realized by combinational logic or a counter having an addition or subtraction function. The pseudo random number generating means 3 is embodied by an M-sequence code generator or the like which is composed of a shift register and an exclusive OR circuit. This output is input to the address terminal of the image memory 8 via the switching means 7. Reference numeral 4 denotes a write address generation circuit, which is a virtual X, Y at a position forming a waveform
The coordinate data is input from the outside and the address of the image memory 8 for storing the virtual X and Y coordinate data is created,
It is input to the address terminal of the image memory 8 via the switching means 7. Reference numeral 5 is a display address generating means for determining which address data in the image memory 8 is to be displayed. The generated address is input to the address terminal of the image memory 8 via the switching means 7. The selecting means 6 selects and outputs the signal from the initial time data generating circuit 1 and the data signal from the change value setting means 2. The switching means 7 selects and outputs the address signal from the pseudo random number generating means 3, the write address generating circuit 4, and the display address generating means 5. The image memory 8 is composed of refresh memories 81 to 8m. Reference numeral 9 denotes a data conversion means, which is a refresh memory 8
It converts m-bit data of 1 to 8 m into a serial signal and includes shift registers 91 to 9 m. Generally, the image memory 8 and the data conversion means 9 are combined and realized by a DRAM having a serial output port. Each address of this DRAM (that is, the refresh memories 81 to 8m in the image memory 8) corresponds to the pixel position of the display, and the data written at that address corresponds to the time after the waveform is written in the pixel. That is, the m-bit data of the refresh memories 81 to 8m at the same address represents the time axis data of the pixel position. Here, the serial output from the data conversion means 9 is output to the display means 11 via the display brightness control circuit 10 for display.

The operation of such a configuration will be described. For the sake of explanation, the structure of the image memory 8 is shown in FIG. In the image memory 8, as described above, each address of the refresh memories 81 to 8m corresponds to the display position. The data at that address corresponds to the time since the first dot was given. The data is m
If it is a bit, 2 ^m kinds of time data can be stored. The numerical value representing the time is not limited to a binary number, and any code system can be used, but here, it will be described as a 4-bit binary number.

First, for understanding, the operation of the entire apparatus will be described. In this device, display (operation of reading waveform data of a plurality of times stored in the image memory 8 and converting it into serial data and drawing it by the display means 11), writing (external C)
Waveform data input from PU, etc. can be displayed on the screen with a virtual X
Position on the axis, Y-axis, whether to draw or not, and the time at which it was written are stored in the corresponding address of the image memory 8), erase (time data at the address of the image memory 8) The operation such as the change, that is, the forcible change of the brightness is performed by time division or parallel processing while arbitrating so that the operation timings of the image memory 8 do not conflict. This arbitration method refers to frame synchronization or horizontal synchronization (hereinafter referred to as CRT) in image processing.
Operation timing) or using a reference clock from the CPU or the like at a timing synchronized or divided, which is the same as a method conventionally used conventionally.

The display operation is as described below. The display address generation circuit 5 creates an address of the image memory 8 in accordance with the operation timing of the CRT, and the selection of the switching means 7 is made the display address generation circuit 5, and this address is inputted to the address terminal of the image memory 8. The image memory 8 reads the data at this address and outputs it to the data conversion means 9. In the data conversion means 9, each of the data is converted into serial data by the shift registers 91 to 9m and sequentially output to the display brightness control circuit 10. The display brightness control circuit 10 creates a voltage corresponding to the brightness based on the data input from the data conversion unit 9 and inputs the voltage to the display unit 11 (CRT or the like). In a normal CRT,
Since the brightness is determined by the voltage of the input display signal, it is possible to display the change in the brightness gradation according to the time data.

The writing operation is as described below. The X and Y coordinates of the point of the waveform to be displayed are input to the write address generation circuit 4 to create the address in the image memory 8. At this address, the value of the data output from the initial time data generation circuit 1 is set to the image memory 8
Then write. The selecting means 6 is switched to output the data of the initial time data changing circuit 1, and the switching means 7 is switched to output the address of the write address generating circuit 5. The data values at this time will be explained in an easy-to-understand manner. It is a 4-bit binary number,
For the sake of simplicity, the numerical value is a decimal number and is expressed as "0". For example, when data “0” is input,
It is understood that the gradation has the highest brightness and the newest waveform. Further, when the data "15" is input, that area is not drawn. The rewriting of this data will be described later.

The erase operation is as described below. An address is a random number generated by the pseudo-random number generator 3 or a number depending on the writing time. An address that depends on a random number is one that randomly selects a portion (pixel) on which a waveform is displayed and reduces the luminance of that portion by one gradation. By this operation, it is possible to display a waveform that does not appear to be artificial so that the fog disappears. The address data output from the pseudo random number generation means 3 is input to the time data change circuit 22.

The time data changing circuit 22 outputs "15" when the input time data has the maximum value "15",
When the input time data is less than "15", the value obtained by adding "1" to the value of the input time data is registered in the register 21.
Output to. The register 21 temporarily stores time data to be written in the image memory 9 again in order to avoid contention on the data bus. This time data is written to the same address in the refresh memory via the selection means 5. Note that, in the embodiment, the time data changing circuit 22 and the register 21 have different configurations, but the register 21 is described.
The use with the time data changing circuit 22 is similar to the operation of the counter, and this part can be collectively realized as a counter.

By such an operation, one-step erasing processing for one selected point (address) (decrease the gradation by one step, and if it is the final gradation of luminance, perform an erasing operation). You can say that). Therefore, when the data is read from the image memory 9 in the next display operation, the changed time data is read. After that one point is displayed on the CRT, it is 15 to completely erase it.
(Type of time-1) It is necessary to perform similar processing for the same point. When erasing only with a random address, if the synchronization of the pseudo-random number matches the number of pixels in the refresh memories 91 to 9n, the number of pixels × 15 times or more and the number of pixels × 16 times or less are used for erasing. Here, for example, 1
One erase operation is performed on us in a screen having 512 × 512 pixels and the time data (luminance gradation) thereof is 4 bits. The erase time of the displayed waveform at this time is from 512 × 512 × 15 × 1us = 3.93 seconds to 512 × 512 × 16 × 1us = 4.19 seconds after the number of pixels is displayed latest. become. That is, the waveform disappears from 3.93 seconds to 4.19 seconds after the waveform is first displayed. To erase the data faster, a faster erase operation is performed. Change the initial time data to reduce the types of time used. The brightness when the value of the time data is large is made to match the brightness of an unused pixel to make it invisible. Etc., and there is a method such as increasing the time interval of an average erase operation for erasing later.

The writing and reading operations of the image memory 8 and the accompanying data will be described. By default,
“15” is stored in the data of each address of the image memory 8. "15" is the maximum value that can be represented by 4 bits, and this value is the value when no waveform data is written or when all the waveform data is erased. At this time, the initial time data generating circuit is assumed to generate "0". That is, the data to be written to the address output from the write address generation circuit 4 in the image memory 8 when the pixel is to be displayed is always "0".

Next, the data stored in the image memory is processed by the above-described method (by reading out the data of the pixel for which the gradation of the brightness is desired to be lowered and changing the data), and the brightness relating to the current time change. It is possible to prevent the discontinuous change of and to erase the brightness randomly.

The image memory 8 is replaced with the refresh memory 8
A 1-bit configuration of only 1 can be used. At this time, since the dot is either written or not written, there is no change in the luminance gradation, and if the address generated by the pseudo random number generation means 3 is used, the waveform is randomly erased. You get the effect. The operation at this time is to leave the read address data in the image memory 8 as it is if it is 1, and change it to 1 if it is 0.
In this case, it is sufficient to set the value to 1 as it is without performing the operation of counting the data, that is, to clear the data, so that the configuration of the change value setting means 2 becomes simpler.

[0018]

As is clear from the above description,
According to the present invention, since the luminance data changes only a part of the screen by the erasing operation, there is no unnatural change in the luminance of the entire screen.

[Brief description of drawings]

FIG. 1 is a configuration diagram of the present invention.

FIG. 2 is an explanatory diagram of an image memory of the present invention.

FIG. 3 is an explanatory diagram of a display screen.

[Explanation of symbols]

 1 initial time data generation circuit 2 changed value setting means 3 pseudo random number generation means 4 write address generation circuit 5 display address generation means 6 selection means 7 switching means 8 data conversion means 9 image memory 10 display brightness control circuit 11 display means

Claims (2)

[Claims] 1. A display image has a two-dimensional array of addresses corresponding to each other on a one-to-one basis, and each address has an image memory in which time data is stored, and a data signal to be input to the image memory. Selecting means, an initial time data generating circuit for inputting a data signal to the selecting means, and a change value for inputting data from the image memory and performing data processing and then inputting a data signal to the selecting means Setting means, a write address generating circuit for generating an address when writing data to the image memory under external control, and a display address generating means for generating an address when reading data for display from the image memory Switching means for switching the signal from the write address generating circuit and the signal from the display address generating means to output to the image memory; Data conversion means for inputting data for display from the image memory and converting it into a signal corresponding to data for display, and outputting the signal from the conversion means as a signal capable of changing the brightness in display. A display brightness control circuit and display means for displaying based on a signal from the display brightness control circuit are provided, and when displaying waveforms with different acquisition times by accumulating and displaying, a gradation step of brightness due to the time difference is smooth. A waveform display and storage circuit characterized in that 2. The waveform display storage circuit according to claim 1, further comprising a pseudo-random number generating means for generating an address for changing the data in the image memory. The means is a pseudo random number generating means, a write address generating circuit, and a waveform display accumulating circuit which is a means for selecting a signal from the display address generating means.