JPH05204588A - Cursor pattern display controller - Google Patents

Abstract

PURPOSE:To display a cursor in a display position of a bit map display device by storing bit map image data to be displayed on the bit map display device and a cursor display pattern. CONSTITUTION:During a flyback time in a screen display of a bit map display device, a cursor display pattern data holding means 2 reads out cursor display pattern data from a prescribed area of a frame memory 1, and holds it in its inside. During a raster scan for displaying a cursor, an image synthesizing/ display means 3 reads out the cursor display pattern data, and bit map image data to be displayed from the frame memory 1, generates a video signal by which the cursor is displayed on the bit map display device by using them, and outputs it to the bit map display device. Accordingly, by utilizing a partial area of the frame memory, its cursor display pattern data is read out of the frame memory, and the cursor can be displayed exactly in the display position of the bit map display device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cursor pattern display control device in a bit map display device.

[0002]

2. Description of the Related Art In graphics display, a frame memory (bitmap memory) for storing display data of each pixel (dot) on the screen in bit correspondence in order to display not only figures and characters but also images in high definition. Often adopts a bitmap display method with.

In this bitmap display system,
It is possible to express by using multiple intricate windows, dynamically move the position of the window, and instantly move a figure to a designated position.

By the way, in the conventional bitmap display device which performs the graphic display by the bitmap display system, the CPU directly draws the mouse cursor pattern in the frame memory by software when the cursor pattern (for example, mouse cursor pattern) is generated. Or bitb which is hardware
This is done by a method such as transferring a small rectangular area in which a mouse cursor pattern is drawn by an lt (bit boundary block transfer) circuit to a frame memory.

However, in each of these methods, it is necessary to perform a process of returning to the original screen and a process of generating a new cursor portion each time the cursor is moved, which increases the load on the CPU and increases the throughput (Throughput) of the system. There is a problem that causes a decrease in.

In addition, in order to compensate for the above-mentioned drawback, there is one having a dedicated RAM for registering a cursor pattern and providing a dedicated circuit for displaying the cursor at an arbitrary position on the screen only by designating a cursor address.

[0007]

However, this method is
Since the cursor can be displayed only by specifying the cursor address, it has the advantages of high speed and no load on the CPU, but it requires a dedicated RAM for registering the cursor pattern, so that the RAM chip There is a disadvantage that the cost is increased by the amount and the RAM chip occupies a predetermined mounting area on the printed circuit board, which makes it difficult to downsize the device.

This shortcoming is due to the use of a dedicated RAM chip to register the cursor pattern. If you try, dedicated R for cursor pattern registration
By eliminating the AM chip, the cost is reduced, and since the mounting area for the dedicated RAM chip is unnecessary, the bitmap display control device can be made smaller and lighter, and the load on the CPU on the host device side can be reduced. If it can be reduced, the throughput of the system will be improved.

An object of the present invention is to use a partial area of a frame memory for storing bitmap image data as an area for registering cursor display pattern data so that the cursor can be displayed at the display position of the bitmap display device. Is to

[0010]

The means of the present invention are as follows. Frame memory 1 (see the block diagram of FIG. 1,
The same applies hereinafter) is a memory for storing bitmap image data and cursor display pattern data to be displayed on a bitmap display device such as a CRT display. The frame memory 1 is composed of, for example, a dual port DRAM (dual port dynamic access memory) having a random port capable of random input / output of data and a serial port capable of serial input / output of data. During the blanking period, for example, during the blanking period immediately before the raster scan for displaying the cursor, the cursor display pattern data holding means 2
The cursor display pattern data for one raster is read out from the frame memory 1 and temporarily held. The image synthesizing means 3 is a bitmap to be displayed during the raster scan for displaying the cursor, and during the raster scan stored in the frame memory 1 and the cursor display pattern data held in the cursor pattern display data holding means 2. The cursor is combined with the image data to generate a video signal displayed at the position on the bitmap display device, and the video signal is output to the bitmap display device such as a CRT display.

[0011]

The operation of the means of the present invention is as follows. The cursor display pattern data holding unit 2 moves the cursor display pattern from a predetermined area of the frame memory 1 during the blanking period in the screen display of the bitmap display device (for example, during the blanking period immediately before the raster scanning for displaying the cursor). Read data and hold it internally. Image composition display means 3
Reads the cursor display pattern data from the cursor display pattern data holding means 2 and the bitmap image data to be displayed in the raster scan from the frame memory 1 during the raster scan for displaying the cursor, and uses those display data. The cursor generates a video signal to be displayed at the position on the bitmap display device and outputs it to the bitmap display device. Therefore,
Using a part of the area of the frame memory that stores the bitmap image data as an area for cursor display pattern data registration, reading the cursor display pattern data from the frame memory, at the display position of the bitmap display device, The cursor can be displayed accurately.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment will be described below with reference to FIGS. FIG. 2 is a circuit block diagram of a main part of the bitmap display control device according to the present invention.

In the figure, a frame memory (FRA
M) 11 is a dual port DRAM (dynamic
Access memory), etc., not shown
Display data (bitmap image data) in the bitmap format to be displayed on the RT display is stored, and cursor pattern data is stored in a part of the storage area. Then, the CPU (not shown) draws the bitmap image data via the data bus 50, the bidirectional bus buffer 51, and the bidirectional bus buffer 61, and displays it on the CRT display via the serial port. The bitmap image data to be output is output to the mixing circuit 37.

Here, the structure of the frame memory 11 is shown in FIG.
Shown in. The frame memory 11 is, as shown in FIG. 3A, a cursor pattern data including a display area 11a for storing display data to be displayed on a CRT display in a bitmap format, mouse cursor pattern data M1 and mask pattern data M2. Storage area 1 for storing
It has 1b.

The mouse cursor pattern data M1 has the format shown in FIG. 3A, and the dot corresponding to the portion showing the shape of the right hand shown in white is "1",
The other parts are set to "0".

Further, the mask pattern data M2 has a format shown in FIG. 9A, and the portion corresponding to the portion having the same shape as the right hand of the mouse cursor pattern filled in black is "1", The other parts are set to "0".

The FRAM controller 12 receives an access request signal to the frame memory 11 from the arbiter 13 and controls the reading / writing of the bitmap image data with respect to the frame memory 11.

The arbiter (ARBITER) 13 receives a plurality of requests from the outside for the frame memory 11, that is, access requests (frame memory access requests),
A plurality of requests such as a refresh request, a data transfer request, and a mouse pattern access request are arbitrated, and a signal corresponding to the received request is output to the FRAM controller 12 or multiplexer (hereinafter abbreviated as MPX) 14. A frame memory access request from a CPU (not shown) is input via the decoder 15.

In the decoder 15, the CPU uses the address bus 4
0 and the address signal output via the buffer 46 are decoded, and the access request (frame memory access request) to the frame memory 11 of the CPU obtained by the decoding is output to the arbiter 13. Arbiter 13
Notifies the CPU of busy (BUSY) via the buffer 45 when the frame memory access request from the CPU overlaps with the other request.

The frame memory start address register (hereinafter abbreviated as FAD register) 16 is a start address VAD of the frame memory 11 via the data bus 50 by the CPU, that is, a bit map to be displayed on the CRT display in the frame memory 11. This is a register in which the head address VAD of the image data is set, and the content (address VAD) is output to a frame memory address counter (hereinafter abbreviated as FAD counter) 17 in the next stage.

The FAD counter 17 is the head of each raster scan in the screen display and the CRT in the raster scan.
A counter that generates the start address of the bitmap image data in the frame memory 11 to be displayed on the display, and counts up by an address equal to the number of words displayed by one raster scan every time one raster scan is completed. .. And at the end of the one-screen display,
The head address VAD of the bitmap image data stored in the FAD register 16 is reloaded under the control of the CPU.

The mouse pattern head address register (hereinafter referred to as MAD register) 18 is used for cursor pattern data (mouse cursor pattern data M) in the frame memory 11 by the CPU via the data bus 50.
1 is a register in which the head address MAD of the storage area of the mask pattern data M2) is set.

Mouse pattern address counter (hereinafter M
An abbreviated as AD counter) 19 sequentially stores the storage address of the mouse cursor pattern data M1 and the storage address of the mask pattern data M2 during the MPH1 during the horizontal blanking time immediately before the raster scanning in which the mouse cursor is displayed.
When output to 4 and the screen display of Mouse Casole is finished, C
Under the control of the PU, the storage address of the mouse cursor pattern data M1 in the frame memory 11 stored in the MAD register 18 is reloaded again.

The addresses generated by the FAD counter 17 and the MAD counter 19 and the address output from the CPU are both output to a multiplexer (hereinafter abbreviated as MPX) 14.

The MPX 14 selects one of the three types of addresses according to the selection signal input from the arbiter 13 and outputs it to the frame memory 11 as an address signal.

A dot counter (hereinafter abbreviated as D counter) 21, a horizontal synchronous counter (hereinafter abbreviated as H counter) 22, and a vertical synchronous counter (hereinafter abbreviated as V counter) 23 are video clock generators. A horizontal synchronizing signal H · SY necessary for screen display by raster scanning on a CRT display is obtained by dividing a clock pulse of a predetermined frequency output from the oscillator (OSC) 20.
The NC and the vertical synchronizing signal V.SYNC are generated.

A horizontal timing controller (hereinafter abbreviated as HT controller) 24 receives an output from the H counter 22 and receives various timing signals (horizontal synchronizing signal H.SYNC, frame memory 11) necessary for horizontal raster scanning. Refresh timing signal, a data transfer request signal to the frame memory 11, and a cursor pattern read timing signal). The refresh timing of the frame memory 11, the data transfer timing to the frame memory 11, and the cursor pattern read timing are respectively the refresh request, the data transfer request, and the cursor pattern read request. Arbiter 13
Output to. Further, the horizontal synchronizing signal H.SYNC is output to the CRT display via the buffer 42.

A vertical timing controller (hereinafter abbreviated as VT controller) 25 receives an output from the V counter 23 and generates a vertical synchronizing signal V.SYNC required for vertical raster scanning, and causes a buffer 43 to operate. Output to the CRT display via.

A vertical cursor position display register (hereinafter abbreviated as MV register) 26 is set with a value indicating a vertical position on the screen of the CRT display where the mouse cursor should be displayed via the data bus 50 by the CPU. It is a register which has a 1-bit mouse cursor display enable designating bit (hereinafter abbreviated as cursor display enable signal) EB indicating whether or not the mouse cursor should be displayed. When the mouse cursor display enable designation signal EB is "1", the mouse cursor display is permitted, and when it is "0", the mouse cursor display is prohibited.

In the horizontal cursor position display register (hereinafter abbreviated as MH register) 27, the CPU sets a value indicating the horizontal position on the CRT display screen where the mouse cursor should be displayed via the data bus 50. The lower 5 bits of the register are output to the shift amount generation circuit 36 as the logical bit shift amount.

Comparison circuit (hereinafter referred to as VCMP) 2
Reference numeral 8 is a digital comparator for detecting that the raster scanning position has become equal to the vertical position where the mouse cursor should be displayed, and the count value of the V counter 23 has become equal to the set value of the MV register 26. When the detection is performed, a coincidence detection signal v for 32 lines of raster scanning (the cursor display pattern has a size of 32 dots × 32 dots in this embodiment) is sent to the AND circuits 30 and 31.

A comparison circuit (hereinafter abbreviated as HCMP) 29 is a digital comparator for detecting that the raster scanning position has become equal to the horizontal position where the mouse cursor should be displayed. When it is detected that the count value of is equal to the set value of the MH register 27, the coincidence detection signal h is output to the AND circuit 3
Send to 1.

The AND circuit 30 receives the cursor detection signal v from the VCMP 28, the cursor display enable signal EB from the MV register 26, and the HT controller 24.
When the control signals from the above are input and all the above three types of signals become active (H level), a mouse pattern access request is output to the arbiter 13.

The AND circuit 31 inputs the coincidence detection signal v output from the VCMP 28, the coincidence detection signal h output from the HCMP 29, and the cursor display enable signal EB from the MV register 26, and all the three types of signals are active. When it becomes (H level), a signal (H level) for instructing the shift amount generation circuit 36 to display a cursor.
Is output.

Mask pattern data register (hereinafter referred to as MS
A register 32 is a 1 in the horizontal direction of the mask pattern data M2 read from the frame memory 11.
It is a 32-bit register that stores data for raster scanning.

In addition, a mouse pattern register (hereinafter MP
The register 33 is a 32-bit register for storing data for one horizontal raster scan of the mouse cursor pattern data M1 read from the frame memory 11.

The mask pattern and mouse cursor data are stored in the MS register 32 and the MP register 33 by using a horizontal or vertical blanking period immediately before raster scanning for displaying the mouse cursor. Be seen.
The mask pattern data M2 of one line, that is, 32 bits, stored in the MS register 32 is output to the barrel shifter 34, and the 32-bit mask pattern data M2 corresponding to the 32-bit mask pattern data M2 is stored in the MP register 33. Mouse cursor pattern data M1
Is output to the barrel shifter 35.

The barrel shifters 34 and 35 shift the 32-bit mask pattern data M2 and the mouse cursor pattern data M1 at the same time by an arbitrary number of logical bits in the right direction, and the shift bit amount generates a shift amount. Provided by circuit 36. The logical bit shift is a shift operation for replenishing empty bits generated by the shift with "0".

The shift amount generating circuit 36 inputs the lower 5 bits of the value set in the MH register 27 by the CPU via the data bus 50 as the shift bit amount. Here, a specific configuration example of the shift amount generation circuit 36 is shown in FIG.

As shown in the figure, the shift amount generation circuit 36
Is a D type flip-flop (hereinafter abbreviated as D flip-flop) 361, 362, an OR circuit 363, exclusive OR circuits (EX / OR) 364 to 368, and +1.
It is composed of an adder circuit 369.

To the data input terminal D of the D flip-flop 361, the output of the AND circuit 31 shown in FIG. 2 (a signal instructing the display of the mouse cursor) is input,
The Q output is output to the data input terminal D of the D flip-flop 362 at the next stage, and the OR circuit 363 is also provided.
Is output to one of the input terminals. A clock for synchronizing the memory cycle of the frame memory 11 is input to the clock terminals C of the D flip-flops 361 and 362. Then, the D flip-flop 36 of the next stage
The Q output of 2 is output to the other input terminal of the OR circuit 363, one input terminal of each of the EX / OR circuits 364 to 368, and the enable terminal E of the +1 addition circuit 369.
N and the barrel shifters 34 and 35 shown in FIG. Each of these EX / OR circuits 364 to 368
To the other input terminal of the MH register 27.
The corresponding 1 bit of the lower 5 bits of the value set to is input. The output of the OR circuit 363 is output to the mixing circuit (details will be described later) 37 shown in FIG.

The shift amount generating circuit 36 receives the signal (H level) instructing the cursor pattern display via the AND circuit 31 (see FIG. 2), and the OR circuit 3
The mixing circuit 37 is activated for a predetermined time via 63, and the Q output of the flip-flop 362 and M
EX-OR circuits 364 to 36 perform exclusive OR with a 5-bit signal indicating the bit shift amount from the H register 27.
8 and outputs the result of the exclusive OR of these 5 bits to the +1 addition circuit 369. Further, the D flip-flop 362 outputs the Q output to the barrel shifters 34 and 35 as a shift direction instruction signal.

The +1 adder circuit 369 receives the Q of the D flip-flop 362 which is input to its enable terminal EN.
When the output is at the L level, the above-mentioned 5-bit exclusive OR output (the above-mentioned 5-bit value) is output. On the other hand, when the above Q output is at the H level, "1" is added to the above-mentioned 5-bit exclusive OR output. The added value (complement of the above 5-bit value) is given to the barrel shifters 34 and 35 as a logical bit shift amount. That is, this logical bit shift amount is to cope with the case where the mouse cursor is displayed over two words as shown in FIG. 3B (in the example shown in FIG. 3B,
(It spans two words "D" and "E" and two words "4" and "5"). In the first memory cycle of the raster scan of the mouse cursor display, the MH register 27 described above is used.
It is equal to the 5-bit value input from, and is equal to the complement of the 5-bit value in the next one memory cycle.

That is, for example, assuming that the 5-bit signal output from the MH register 27 is "0", "0", "0", "1", "1" from the upper bit direction, the mouse cursor is first. In the first memory cycle of the first display, the EX-OR circuits 364 to 368 allow the 5-bit signal and the D-type flip-flop circuit 36 to operate.
An exclusive OR with the Q output of 2 (Q = “0” at this point) is obtained, and the exclusive OR output is “0”,
It becomes "0", "0", "1", "1". Therefore,
The logical bit shift amount in the right direction (horizontal scanning direction) of the 32-bit mouse cursor pattern data M1 in the horizontal scanning direction in the first memory cycle for displaying the mouse cursor is “3” (see FIG. 7A). .. Since the Q output of the flip-flop 362 becomes "1" in the second memory cycle of the second mouse cursor display, the exclusive OR outputs are "1", "1", "1", "0". ，
It becomes "0", and the value obtained by adding "1" to the above value is 5
Complement of bit value "29" (= "1", "1",
"1". "0", "1") is the logical bit shift amount in the left direction (anti-horizontal scanning direction) of the 32-bit mouse cursor pattern data M1 in the second one memory cycle (FIG. 7B). reference).

The barrel shifters 34 and 35 are respectively MS
The 32-bit mask pattern data M2 input from the register 32 and the mouse cursor pattern data M1 input from the MP register 33 are input to the shift amount generation circuit 36 in the first and second memory cycles of mouse cursor display. The logical bit shift amount input from the above is sequentially shifted to the right and to the left, and the display data and the mask data of the mouse cursor obtained thereby are output to the mixing circuit 37.

The mixing circuit 37 uses the mask data to display the mouse cursor display data and the 32-bit bitmap image data (background pattern) output from the serial port of the frame memory 11 as described later in detail. Image synthesis is performed, and 32-bit (32 dot) bitmap image data obtained by the screen synthesis is output in parallel to a parallel / serial conversion circuit (hereinafter abbreviated as P / S conversion circuit) 38.

The P / S conversion circuit 38 converts the 32-bit parallel bitmap image data into serial 32-bit (32 dot) bitmap image data,
The video signal is output to the CRT display via the buffer 41.

The mixing circuit 37 is, specifically,
For example, as shown in FIG. 5, AND circuits 371 and 37
A circuit 370 composed of 2, 373 and an OR circuit 374 displays a mouse cursor in 3 in one memory cycle.
32 dots are arranged in parallel corresponding to the display of each dot of 2 dots.

In the circuit 370, the AND circuit 37.
One of the input terminal 1 receives the corresponding predetermined 1-bit data of the mask pattern data M2 logically shifted by the predetermined amount by the barrel shifter 34, and the other input terminal receives the shift amount generation circuit 36. Start signal (H
Active at level) is entered. The output of the AND circuit 371 is input to one input terminal of the AND circuit 372 and also output to one negative logic input terminal of the AND circuit 373.

Further, the other input terminal of the AND circuit 372 receives the corresponding predetermined 1-bit data of the mouse cursor pattern data M1 which has been logically shifted by the predetermined bit amount by the barrel shifter 35, and the AND circuit 372. Takes the logical product of the 1-bit data of the mouse cursor pattern data M1 and the output from the AND circuit 371, and outputs the result of the logical product to the OR circuit 374.

Further, the other predetermined input 1-bit data of the 32-bit bitmap image data (background pattern) read from the frame memory 11 is input to the other input terminal of the AND circuit 373. Therefore, the 1-bit bitmap image data input from the frame memory 11 is output to the OR circuit 374 by the AND circuit 373 when the bit of the mask pattern data M2 input from the barrel shifter 34 is "1". The mouse cursor pattern data M1 is forbidden and replaced with P by way of the AND circuit 372 and the OR circuit 374.
It is output to the / S conversion circuit 38.

On the other hand, when the bit is "0", the AND circuit 372 prohibits the output of a predetermined bit of the mouse cursor pattern data M1 output from the barrel shifter 35. Instead, the 32-bit bitmap image data is output. One predetermined bit of the above is output to the P / S conversion circuit 38 via the OR circuit 374.

Therefore, the bitmap image data (background pattern) is erased by masking the portion corresponding to "1" of the mask pattern data M2, and the mouse cursor is displayed at the erased portion.

Next, the operation of the bitmap display control device having the above configuration will be described with reference to FIG. In the screen display by raster scanning on the CRT display, as shown in FIG. 6, there are horizontal and vertical blanking periods (blanking blanking periods) and display periods, and the display is not performed by the normal mouse cursor. In the blanking period immediately before the period, immediately before switching to the display period in the blanking period as shown in FIG. 7A, refresh of the frame memory 11 composed of DPRAM (dual port RAM) and the CPU Two memory cycles of data transfer for writing / reading bitmap image data to / from the frame memory 11 via the random access port are continuously executed.

On the other hand, in the blanking period immediately before the display period in which the mouse cursor is displayed, the free time in the blanking period is used as shown in FIG. In the first two memory cycles in, the mouse cursor pattern data M1 and the mask pattern data M2 to be displayed in the subsequent display period are sequentially read from the frame memory 11 in advance and held in the MS register 33 and the MS register 32, respectively. Then, in the above display period, while the raster scanning position is the display position of the mouse cursor, the processing for synthesizing the mouse cursor pattern data M1 and the bitmap image data by the mixing circuit 37 as described above is performed by the hardware. The operation is performed, and the mouse cursor is displayed on the relevant part of the display screen of the bitmap image data.

The operation during the display period shown in FIGS. 6A and 6B will be described in more detail. First, during the display period in which the mouse cursor is not displayed, the cursor enable designation signal EB is set to "0", so the arbiter 13 accepts the data read request from the HT controller 24, and the MPX 14 and FRAM controller. Control twelve. MPX14 is Arbiter 13
The count value of the FAD counter 17 is selectively output to the frame memory 11 as an access address signal in response to a selection signal added from. As described above, the count value of the FAD counter 17 is a counter for generating the storage address of the bitmap image data to be read from the frame memory 11 and transferred to the mixing circuit 37.
Therefore, by the above-described operation, the storage address of the 32-bit bitmap image data to be displayed next is output from the MPX 14 to the frame memory 11, and subsequently the FRAM controller 12 outputs a data read control signal to the frame memory 11. To do.

As a result, the 32-bit bitmap image data of the serial port of the frame memory 11 is read and serially transferred to the mixing circuit 37.
In the cursor display instruction signal output from the AND circuit 31, the cursor enable designation bit EB is "0".
Since it is inactive (L level), this 32-bit bitmap image data is directly passed through the mixing circuit 37 to the P / S conversion circuit 38.
After being sent to the CRT, the P / S conversion circuit 38 performs serial conversion and outputs the serial video signal to the CRT display.
The screen is displayed on the RT display.

The operation of this one memory cycle is
The bitmap image for one horizontal scan is displayed by being repeated a predetermined number of times during the display period in which the cursor is not displayed.

Next, the operation for displaying the cursor pattern will be described. When the cursor pattern is displayed, the cursor enable designation signal EB is set to "1". Then, in the first memory cycle of the blanking period immediately before the display period in which the mouse cursor is displayed, the VCM
The V-direction coincidence signal (“H” level) is output from P20, and the mouse cursor data read timing signal is output from the HT controller 24. As a result, the AND circuit 30 outputs a cursor pattern access request to the arbiter 13.

Upon receiving this request, the arbiter 13 causes the MPX 14 to selectively output the count value of the MAD counter 19 (the storage address MAD in the frame memory 11 of the mouse cursor pattern data M1) to the frame memory 11 as an access address. Then, after the output of this access address, the arbiter 13 operates in the FRAM.
A data read control signal is output to the frame memory 11 via the controller 12, and as shown in FIG. 6B, in the first one memory cycle of the blanking period immediately before the display period in which the cursor is displayed, The mask pattern data M2 is read from the memory 11 and the MS register 3
Store in 2. Then, at the start of the subsequent memory cycle, the value of the MAD counter is incremented by "1", and the value is output to the frame memory 11 via the MPX 14 as an access address. Then, similarly to the case of the mask pattern data M2, the mouse cursor pattern data M1 is read from the frame memory 11, and the mouse cursor pattern data M1 is read by the MP register 3
3 is stored.

As described above, the MS registers 32, M
The respective pattern data held in the P register 33 are logically bit-shifted by the bit shift amount generated by the shift amount generation circuit 36 by the barrel shifters 34 and 35.

This logical bit shift is performed by using the lower 5 bits of the value set in the MH register 27 as described above, but the shift amount generation circuit 36 causes the mouse cursor to extend between two words. When displayed, the detection signal output by the VCMP 28 when the horizontal raster scanning position matches the display position of the mouse cursor is input as a cursor pattern display instruction signal via the AND circuit 31 (at this time, the output of the HCMP 29 is output). The detection signal to be activated is already active (H level), and the 5 bits are complemented in the first memory cycle of the mouse cursor display, and the complement of the 5 bits is implemented in the second memory cycle in the reflex shifters 34 and 35. Output.

Here, this operation will be described in more detail with reference to FIG. 7, taking the case where the bit shift amount is “3” as an example. In the case of this example, the MH register 27
Since the value of the lower 5 bits of the bit shift amount is “3”, “0”, “0”,
“0”, “1”, “1”, and the 5-bit value is input to one of the corresponding input terminals of the EX / OR circuits 364 to 368 of the shift amount generation circuit 36. Then, the Q output of the first-stage D flip-flop 361 becomes "1" at the time of the first read of one memory cycle, and the Q output of the next-stage D flip-flop 362 at the time of the next second read of the one memory cycle. It becomes "1".

Therefore, in the first one memory cycle, the state of the other input terminal of each EX.OR circuit 364-368 is "0", and each EX.OR circuit 364-36.
8 outputs "0" from the MH register 27,
The 5-bit signals of “0”, “0”, “1”, and “1” are directly passed through the +1 addition circuit 365 to the shift amount generation circuit 36.
The Q output of the D flip-flop 362, which is output to the shift amount generation circuit 36 as a shift direction instruction signal, becomes "0". As a result, the barrel shifters 34, 35
Shifts the 32-bit mouse cursor pattern data M1 and the 32-bit mask pattern data M2 input from the MS register 32 and the MO register 33, respectively, to the right by 3 bits (see FIG. 7A). Therefore, in the first memory cycle, the mouse cursor
The right 29 dots are displayed. Then, the second one
In the memory cycle, the remaining 3 dots on the left side of the mouse cursor that have not been displayed are displayed.

In the second one memory cycle, the Q output from the D flip-flop 362 at the next stage becomes "1", and the Q output is input to the other input terminals of the EX.OR circuits 364 to 368. .. As a result, the EX-OR circuits 364 to 368 output the 5-bit outputs “0”, “0”, “0”, “1”, and “1” from the MH register 27 and the Q output of the D flip-flop 362 to the 5-bit outputs. "1" of
An exclusive OR operation with "1", "1", "1", "1" is performed, and the result of the exclusive OR "1", "1",
"1". “0” and “0” are output to the +1 addition circuit 365. Then, the bit shift amount “3” (“0”, “0”, “0”, “1”,
"29" (= "1", "1", which is the complement of "1")
"1", "0", "1") is generated as a bit shift amount and output to the barrel shifters 34, 35.

In this way, the mouse cursor pattern data M1 and the mask pattern data M2 are logically bit-shifted by a predetermined bit amount corresponding to the mouse operation, and then read from the frame memory 11 by the mixing circuit 37 as described above. The generated bitmap image data and the mouse cursor pattern data M1 obtained by the logical bit shift are subjected to image synthesis using the mask pattern data obtained by the logical bit shift, and further obtained by the image synthesis. The 32-dot parallel bitmap image data is serially converted by the P / S conversion circuit 38 and serially output as a video signal to the CRT display.

By the above operation, the mouse cursor is displayed on the screen of the CRT display over the two words as shown in FIG. 7B. in this way,
In this embodiment, a part of the frame memory 11 is replaced with mouse cursor pattern data M1 and mask pattern data M2.
Of the mask pattern data M2 and the mouse cursor pattern data M1 are sequentially read from the frame memory 11 during the blanking period immediately before the horizontal raster scan reaches the raster position for displaying the mouse cursor. The respective pattern data are temporarily held in the MS register 32 and the MP register 33, respectively. The bitmap image data read from the frame memory 11 and the MP register 33 while the horizontal raster scanning position is the display position of the mouse cursor.
The mouse cursor pattern data M1 held in 1 is image-synthesized using the mask pattern data M2 held in the MS register 32, and the mouse cursor is displayed on the CRT display.

Therefore, the dedicated RAM chip for storing the cursor pattern data is not required, and the mouse cursor display control can be performed at high speed by hardware by adding a simple circuit.
It is possible to display the mouse cursor while significantly reducing the load on U.

In the above embodiment, the mask pattern data M1 and the mouse cursor pattern data M2 are read from the frame memory 11 in the first two memory cycles of the blanking period. The read timing is not limited to this, and it may be performed in any period as long as it is a free period in the blanking period.

The cursor display may also be performed by another method that does not use the mask pattern data.

[0071]

According to the present invention, a partial area of a frame memory for storing bitmap image data is used as an area for registering cursor pattern data, and the cursor pattern is read from the frame memory to display the display position. I made it possible to display the cursor accurately on,
The dedicated RAM chip for registering the cursor pattern is not required, so the cost is reduced, and since the mounting area of the dedicated RAM chip is not required, it is possible to reduce the size and weight of the bitmap display control device, and further, the host device. Since the load on the side CPU is reduced, the system throughput is also improved.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a configuration diagram showing a cursor pattern display device according to an embodiment.

FIG. 3 is a configuration diagram of a frame memory in the above embodiment.

FIG. 4 is a circuit configuration diagram of a shift amount generation circuit in the above embodiment.

FIG. 5 is a circuit configuration diagram of a mixing circuit in the above embodiment.

6A and 6B are views for explaining a display operation of one line by raster scanning in the above embodiment, FIG. 6A is a view for explaining an operation when cursor display is not performed, and FIG. 6B is a cursor display. It is a figure explaining operation | movement when performing.

FIG. 7 is a diagram illustrating a shift operation of cursor pattern data in the above embodiment.

[Explanation of symbols]

 1 frame memory 2 cursor display data holding means 3 image composition means

Claims (2)

[Claims] 1. A frame memory for storing bitmap image data to be displayed on a bitmap display device and cursor display pattern data, and reading the cursor display pattern data from the frame memory during a blanking period of raster scanning. Cursor display pattern data holding means for holding and cursor display pattern data held in the cursor display pattern data holding means and raster scan stored in the frame memory during raster scanning An image synthesizing unit for synthesizing the bitmap image data to be synthesized and generating and outputting a video signal in which the cursor is displayed at the position on the screen of the bitmap display device. apparatus. 2. The cursor display pattern data holding means reads one cursor of the cursor display pattern data from the frame memory during a blanking period immediately before raster scanning for displaying a cursor.
The cursor pattern display control device described.