JPS6292991A - Image display system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Technical field The present invention relates to an image display method.

BACKGROUND ART Display devices used in audio equipment installed in automobiles, for example, are equipped with cathode ray tubes, and the operating status of the audio equipment is displayed using the cathode ray tubes. Cathode ray tubes used for such applications have a flat, ie, horizontally elongated display area compared to the 3×4 display area of cathode A tubes used in TV Noyon reception stations in the United States.

Problems to be Solved by the Invention When displaying images from TV Noyon reception using a cathode #X tube having such a horizontally long and flat display area,
If one line's worth of image signals is displayed during the same horizontal scanning period, the image will be horizontally long and flat, making normal display impossible.

An object of the present invention is to provide an image display method that can display an image in an area with a desired aspect ratio.

Means for Solving the Problems The present invention writes image signals during each horizontal scanning period into a pair of memories alternately for each horizontal scanning period, and writes the image signals from one of the pair of memories to which no writing has been performed. This image display method is characterized in that the image is read out and displayed within a period that is the same as or shorter than the horizontal scanning period.

According to the present invention, from among a pair of memories, from the memory that stores the content written during the previous horizontal scanning period, the horizontal scanning period at the time of writing is the same or shorter than the previous horizontal scanning period. When one memory is read, the other memory is written, and the image is displayed in this way. Therefore, the horizontal scanning period at the time of readout can be set to the desired value. This makes it possible to select the aspect ratio of the image display area to a desired value.

Example FIG. 1 is a block diagram of one embodiment of the present invention.

The image signal 1 generation circuit 50 is shown in FIG. 2 (1).
To display an image with an aspect ratio Al/Bl, a write clock is applied to line 50 for each dot during each horizontal scan period.
Derived as follows. A vertical synchronization signal is derived from line 32, and a horizontal synchronization signal is derived from line 33. The period of the horizontal synchronization signal is 63.2 μsec, and the vertical synchronization signal also serves as the horizontal synchronization signal for the first horizontal scanning line of the image. An image signal for each horizontal scanning period is derived from line 18. The image signal from such an image signal generation circuit 50 is t! as shown in FIG. 2 (2). 1 side ratio A2/
In the cathode ray tube 34 having a display area having B3,
It is displayed in a shaded area 35 with an aspect ratio of A 2 /B 2 . The aspect ratio A2/B2 of this area 35 is shown in FIG.
It is equal to the aspect ratio Al/B1 of the image shown in 1), and is, for example, 3/4. In order to display images in such areas with different aspect ratios, according to the present invention, a pair of line memories M 1 are provided to store image signals for each single horizontal set meal line.

M2 is provided.

Horizontal sync number 43 is derived on line 3-3 as previously described. This horizontal synchronizing signal has the waveform shown in FIG. 3 (1) 1. The one-shot circuit 2 receives the horizontal synchronizing signal and derives the pulse shown in FIG. 3 (2) having a smaller pulse width. do. Similarly, the pulse width of the vertical synchronizing signal from the line 32 is reduced by the one-shot circuit 1. The output from the one-shot circuit 1.2 is input to an OR date 3 forming a write address generator 36. The output from OR date 3 clears 8-bit counter 4. This counter 4 is provided with a write clock via line 51. Counter 4 is thus cleared every horizontal open period and counts the write clocks from line 31.

The output from the counter 4 is input through a line 37 to a write start detection date 6 and a write end detection date 8 provided in the write signal generator 5. Write start detection date 6 is determined at time t2 when the count value of counter 4 reaches a predetermined value after time t1 (see Figure 3 (4)).
7rip 70 knob 7 is set at the write completion detection date 8, when the contents of the counter 4 reach a predetermined value at time L5 after time t2. . The 7-rip prop 7 thus derives from the output terminal Q on line 38 the signal shown in FIG. 3(3). The signal from line 38 is applied to input terminals C8I and C32 of memories M 1 and M 2 , and when the signal on line 38 is at a low level,
Memories M1 and M2 are activated by so-called chip selection.

The read address generator 10 outputs OR dates 11 and 1.
It has an 8-bit counter 12, the outputs from the one-shot circuits 1 and 2 are given to the OR date 11, and the counter 12 is cleared by the output from the OR date 11. A read clock from a read clock generator 39 is supplied to the counter 12 via a line 40 . The read clock generator 39 includes an oscillator 41 and the oscillator 4
It has an output of 1 and a counter 42 that divides the frequency. Counter 42 is cleared by the output from OR date 11. The read tally derived from this counter 42 on line 40 has a higher frequency compared to the write clock on line 51, i.e. the horizontal scan period of the read clock on line 40 is less than the horizontal scan period of the write clock on line 51. . In another embodiment of the invention, the horizontal scanning periods of the write clocks on lines 51, 40 may be the same.

The output from the OR date 11 is the read/write switching circuit 14.
It is given to the torgue lip 70p 15 provided in the. As a result, the torque lip 70 knob 15 is
Each time a pulse from R date 11 is applied, the stable state is reversed as shown in FIG. 3 (12). In the first horizontal scanning period after time 1, there are 7 rips, 70 rips, and 15 rips.
Assume that the output Q of is at a level of 1. At this time, the data selector 16 connects the input terminal A1 to the output terminal Y1.
The input terminal A2 is electrically connected to the output terminal Y2. During the second horizontal scanning period after time 〇 when the output Q of the 7-rip 70-tube 15 is at a low level, the input terminal B1 of the data selector 16 is electrically connected to the output terminal Y1.
Input terminal B2 is electrically connected to output terminal Y2.

The output Q of the 7-rip 70-rub 15 is also the r of the memory M1.
The signal is applied to a data selector 30 which performs address designation. When the output Q of the 7-lip 70-tube 15 is at a high level, the input terminal A of the data selector 30 conducts to the output terminal Y, and when the output Q of the 7-lip 70-tube 15 is at a low level, the input terminal B conducts to output terminal Y.

The low level signal at time 2 to L5 derived from the 7-lip 70 block 7 in the write signal generator 5 to the line 38 is transmitted from the input terminal A1 of the data selector 16 to the output terminal Y1 from the line 43 to the memory M1. It is input to the input terminal WEI, and a write operation becomes possible. The signal on this line 43 is as shown in FIG. 3(4).

The signal on line 43 is also applied to input terminal C33 of tri-state output terminal 7a 20 of circuit 19 which performs switching of write data. Since the signal on the line 43 is at a low level, the part 7a 20 sends the image signal from the line 18 to the memo IJM via the line 44.
Enter 1. The image signal generation circuit 50 derives the image No. 41 for one horizontal fabrication line in the image area shown in FIG. 2(1) during the period from time t2 to time L5. The address signal derived from the write address generator 36 on the line 37 is input to the memory M1 from the input terminal A of the data selector 30 via the output terminal Y. At this time, the signal is applied via line 44 from input terminal A2 of data selector 16 to output terminal Y2. The high level signal is applied to the input terminal OE1 of the memory M.

When the input terminal OEI of the memory M1 is at high level,
No read operation is performed. The signal waveform of line 53 is as shown in FIG. 3(5).

In this manner, the memory M1 writes the image signal from the buffer 20 into the store area addressed by the signal from the data selector 30 at times t2 to L5.

The output from the read address generator 10 is on line 45.
The output of these output dates 24 and 25 sets and resets the 7-lip 70-tub 26.

The reset output Q of the 7rip 70rub 2G is on line 46.
and is applied to the input terminal B2 of the write data selector 16. During the first horizontal scanning period from time 1 to t6, the output Q at the 7-lip prop 15 of the read/write switching circuit 14 is at a low level, so the input terminal B of the address data selector 31 is electrically connected to the output terminal Y. .

This address data selector 31 selects the input terminal A when the output Q of the 7-lip 70-tub 15 is at the level of
conducts to output terminal Y.

The input terminal W E 2 of the memory M2 is supplied with a signal fi from a line 43 to the inverting circuit 22 . Memory M
A signal having a waveform shown in FIG. 3 (7) is applied to the input terminal WE2 of No. 2.

No. 13 from line 38 is applied to chip select input terminal C32 of memory M2, and its waveform is fjS3.
As shown in Figure (6).

The read input terminal OE2 of the memory M2 receives four outputs from the NAND date 28, and its waveform is shown in the rjS3 diagram (8).
) as shown. As mentioned above, the signal shown in FIG. 3 (7) from the inversion circuit 22 is input to the NAND date 28, and the signal shown in FIG.
The signal shown in FIG. 3 (11) from the output Q of the lip 70 tube 26 is inverted and applied by the inverting/inverting circuit 27. During the first horizontal scanning period of ~L6, the output terminal Y2 of the data selector 16 of the reading switching circuit 14 is electrically connected to the input terminal A2, and a high-level equal signal is output to the 2-in 44. be done. In this way/
The readout input terminal T-01E2 of the memory M2 is connected to the
8) From NAND date 28 to time L2
At ~L4, the low level (, -17- is given, which causes a period of
The contents of 2 are read out.

The memory M21 is supplied with an address signal from line 45 through the input terminal B and output terminal Y of the address data selector 3, and the contents of the memory M2 are read out based on this address signal.

The output from the inverting circuit 22 is applied to the tri-state output pin 7a 21 for switching the image signal for image processing, and its signal waveform is as shown in FIG. 3 (10). The buffer 21 is 1 in the period from 2 to t5.
1.

The output on line 4.t is seen from the inverting circuit 29 to the data selector 55 for readout switching.

The data selector 55 conducts the input terminal T-8 and the output terminal 7-Y when the outputs from the two inverting circuits are low level, and connects the input terminal A and the output terminal Y when the outputs are high 1/bell.
Conducts with. During the horizontal scanning period from time 2 to 1G, the data selector 55
5 is seen in the latch circuit 47 for waveform shaping from the input terminal B to the output terminal FY. The latch circuit 47 is supplied with a clock from the readout clock generator 39 via the line 40, which causes the waveform to be shaped into the drive circuit 4.
8 to the cathode ray tube 34. Furthermore, in the first horizontal scanning period from time 1 to t6, time 2
~In L5, the image signal is written to memo 17 M+/
1. From time t3 to t4, eight of the memo 'JM2' are read out and displayed in a readout period that is the same as or shorter than the rereading period according to the tarok from the three readout clock generators.

During the next second horizontal scanning period from time 6 to Lll, one output Q of the 7-lip 70-tube 15 of the read/write switching circuit 4 becomes a low level, and the output Q becomes a high level. Therefore, the signal from the built-in address generator 36 is
7 is applied to the input terminal of the data selector 31 and to the memory M2 via the output terminal Y. During the period from time 7 to tlo when the input terminal W E 2 of the memory M2 is at a low level, the image signal from the line 18 is transferred to the buffer 21.
The image signal is applied to the memory M2 via line 49, thereby writing the image signal into the memory M2.

Also, during this second horizontal scanning period 6 to L11, the number from the read address generator 10 is transmitted from the line 45 to the input terminal B of the data selector 30 and the output terminal Y.
and stored in memory M1. At times t8 to t9, the signal from the output terminal Y2 of the data selector 16 via the line 53 is at a low level, so that the memory M1
The stored contents are read out during the period from time 8 to t9. During the second horizontal scanning period from 6 to tll, the outputs of the two inversion circuits are at a high level during the period from time t8 to L9, and therefore the input terminal A of the data selector 55
conducts to output terminal Y. The image warp code thus read out from the memory M is waveform-shaped by the data selector 55 and the latch circuit 47, and is displayed on the hidden line tube 34 by the action of the drive circuit 48.

From time tt1 onward, during the third horizontal scanning period i, the same operation as the first horizontal scanning period shown from 1 to t6 is performed, and furthermore, at the subsequent fourth horizontal scanning period, time t
The operations from time 6 to time 11 are performed, and the operations from time 1 to time 111 are repeated in the same manner.

Effects As described above, according to the present invention, the stored contents of the memory for memory (i) are read out during the period when one of the pair of memories is being written, and the read speed is set to a desired value. Therefore, it is possible to display both image distribution areas with different vertical and horizontal ratios.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram for explaining the display operation of the cathode ray tube 34, and FIG. 3 is a waveform diagram for explaining the operation. 1.2...Funshot circuit, 5...Write signal generator, 10...Address generator for reading, ]4...Read, 1'i switching circuit, 19...Data switching for writing Circuit, 23... Read signal generator, 30.31.
...Address data selector, 3...Read clock generator, 50...Image signal generation circuit, Ml, M2...
・・Line Memory Agent Patent Attorney Kei Shikyo Part 2 Figure 2

Claims (1)

[Claims] Image signals during each horizontal scanning period are written alternately to a pair of memories for each horizontal scanning period, and from among the pair of memories, the memory to which writing is not performed is performed within a period that is the same as or less than the horizontal scanning period. An image display method characterized by reading out and displaying images.