JPH01170985A - Character display device - Google Patents

Abstract

PURPOSE:To preclude a flicker on a screen by providing a timing adjusting circuit. CONSTITUTION:Even when write data is supplied from a microcomputer 28, writing operation is not started immediately and a write signal is latched temporarily and supplied to a display data RAM 21 for a horizontal blanking period. Consequently, the display data RAM 21 is rewritten in horizontal blanking periods, namely, on an ineffective screen. Further, data is inhibited from being written in this period so that next data is written while the write signal is delayed to a next horizontal blanking period. Therefore, data are prevented from being rewritten on an effective screen, and consequently the flicker on the screen is eliminated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides display data RAM (Random Ac
This invention relates to a character display device that displays a character by scanning a character code stored in a cessMemory and also rewrites the display data as needed by rewriting the data in the display data RAM by a microcomputer, especially preventing flickering when rewriting the display data. The present invention relates to a character display device.

[Prior Art] Generally, a character display device has a display data memory and a CR.
The display operation is performed by direct memory access with display means such as T, and the contents of the display data memory are accessed from the microcomputer.
It is configured to be rewritable at any time.

FIG. 3 is a block diagram showing a conventional character display device of this type. In the 0 display data RAM II, codes of characters to be displayed are stored in correspondence with display positions on the display screen. The scanning address given to this display data RAMII, that is, the row selection signal and the digit selection signal, are generated by the vertical address counter 12 and horizontal address counter 13 from the horizontal synchronization signal and the oscillation circuit 14 synchronized with this horizontal synchronization signal. is given by counting the respective dot clock signals. The code in the display data RAM II scanned and read by this is stored in the character generator ROM (Read Only M
memory) 15. The character generator ROM 15 outputs a character pattern corresponding to the given code, which is serially converted in the character pattern serial output shift register 16 based on the dot clock signal and output as a character output signal to the CRT display 17. Is displayed.

On the other hand, the display data RAM is stored from the microcomputer 18.
When display data is rewritten to RAM II, first, the write address from the microcomputer 18 is stored in the write address register 19, then the write data is given to the display data RAM II, and the data selector 20 is The selected address is switched from the scanning address to the write address, and this write address is applied to the display data RAMII.

Then, data is written into the display data RAMII by a load signal from the microcomputer 18.

[Problems to be Solved by the Invention] The above-mentioned conventional character display device uses display data RA.
Since the configuration is such that data can be written to M at any time, if display data is written on the valid screen,
When writing data, the display data to be rewritten appears on the screen, causing flickering.

The present invention has been made in view of such problems, and includes:
To provide a character display device which can prevent flickering on a screen when rewriting display data and has excellent display quality.

[Means for solving the problems] The present invention provides a display data RAM that stores display data;
a scan address generation circuit that generates and outputs a scan address;
Normally, a scan address is given to the display data RAM, and when write data from the microcomputer is given, a selector that supplies the write address from the microcomputer to the display data RAM, and a selector that supplies the write data from the microcomputer to the display data RAM. In a character display device that includes a character generator that generates and outputs a character pattern from a code, and a display signal generation circuit that generates a display signal from the character pattern, when write data is given from the microcomputer, the A write signal is latched and applied to the display data RAM during the horizontal retrace period, and a signal is output to the microcomputer to inhibit writing of the next data from the microcomputer during the period in which the write signal is latched. It is characterized by being equipped with a timing adjustment circuit.

[Operation] According to the present invention, even if write data is given from the microcomputer, the write operation is not immediately started, but the write signal is latched once and then transferred to the display data RAM during the horizontal retrace period. I try to give it to Therefore, the display data RAM is rewritten during the horizontal retrace period.
That is, it is performed on an invalid screen. Furthermore, in order to prevent the next data from being written while the write signal is delayed until the next horizontal retrace period, the present invention prohibits data writing during this delayed period. .

The above-described effects can prevent data from being rewritten on the valid screen, thereby preventing flickering on the screen.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram of a character display circuit according to this embodiment. The display data RAM 21 stores codes of characters to be displayed in correspondence with display positions on the display screen. The scanning address of this display data RAM 21 is
Vertical address counter 22 and horizontal address counter 23
is given by. The vertical address counter 22 counts the horizontal synchronizing signals and outputs a row selection signal for the display data RAM 21. This row selection signal is a signal that specifies a row address in the vertical direction on the screen, and is reset by a vertical synchronization signal. The horizontal synchronization signal is given to the oscillation circuit 24. The oscillation circuit 24 frequency-multiplies the horizontal synchronizing signal to generate and output a dot clock signal. The horizontal address counter 23 counts this dot clock signal and outputs a digit selection signal for the display data RAM 21. This digit selection signal is a signal that specifies a digit address in the horizontal direction on the screen, and is reset by the horizontal synchronization signal.

These row selection signals and digit selection signals are sent to the display data RAM 21 via the data selector 30 as scanning addresses.
given to.

The display data RAM 21 outputs a character code corresponding to one digit of the row selected by the row selection signal and the digit selection signal, and supplies it to the character generator ROM 25. The character generator ROM 25 generates a character pattern signal corresponding to the given code. The character pattern serial output shift register 26 reads the character pattern signal and outputs a character signal synchronized with the dot clock signal to be displayed on the CRT 27.

On the other hand, in order to rewrite the display data, the write address (row 1 digit) output from the microcomputer 28 is given to the write address register 29. When the write address is set in the write address register 29, the microcomputer outputs write data, which is applied to the display data RAM 21. Subsequently, a load signal (write signal) output from the microcomputer 29 is applied to a timing adjustment circuit 31.

The timing adjustment circuit 31 adjusts the output timing of the write signal to the display data RAM 21, and
During this adjustment, if writing of the next data to the microcomputer 28 is prohibited, a gee signal is output. This timing adjustment circuit 31 includes NOR gates 32 and 33.
RS flip-flop 34 consisting of
5 and a delay circuit 36. The load signal from the microcomputer 28 sets the output of the RS flip-flop 34 and is applied to one input of the AND gate 35. The other input of the AND gate 35 has
A horizontal synchronization signal is provided. Therefore, AND gate 35
From then on, the load signal latched by the RS flip-flop 34 is output at the output timing of the horizontal synchronizing signal, and this is given as a write signal to the display data RAM 21.

At this time, the data selector 30 operates to select the write address. Further, the horizontal synchronizing signal is delayed by about 10 μs in the delay circuit 36, and the RS flip-flop 34
This becomes the reset signal. From the time the RS flip-flop 34 is set until it is reset, the output of the RS flip-flop is given to the microcomputer 28 as a busy signal. The microcomputer 28 does not write the next data while the G signal is being input.

FIG. 2 is a timing chart showing the output timing of each part of this device in comparison with that of a conventional example.

Conventionally, since writing to the display data RAM was performed regardless of the horizontal synchronization signal, flickering occurred on the screen when data was rewritten on the valid screen. but,
In the device of this embodiment, since data writing coincides with the horizontal synchronizing signal, rewriting is performed on an invalid screen. Therefore, there is no effect on the screen at all. Further, since writing of the next data is prohibited from generation of write data to writing, no data is lost due to continuous application of data.

In the above embodiment, the timing adjustment circuit includes the RS flip-flop 34, the ANDNO gate, and the delay circuit 36.
However, this is an example, and for example, 63.5
A monostable multivibrator set to a pulse width of μs is triggered by a load signal from a microcomputer,
The output and the horizontal synchronization signal are given to the AND gate and the RA
It is also possible to obtain M write signals, and various other circuits can be considered that can achieve the same function.

[Effect of the invention - As explained above, the present invention adds a timing adjustment circuit so that even if a load signal is sent from the microcomputer on the valid screen, data is written on the invalid screen. This has the effect of preventing flickering on the top.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a character display device according to an embodiment of the present invention, and FIG. 2 is a display data RAM 21 of the device.
FIG. 3 is a block diagram showing a conventional character display device. 11.21; Display data RAM, 12.22; Vertical address counter, 13.23. horizontal address counter, 1
4.24. Oscillation circuit, 15, 25; Character generator ROM, 16.26; Character pattern serial output shift register, 17.27. CRT, 18, 28
; Microcomputer, 19.29; Write address register, 20.30. Data selector, 31; timing adjustment circuit, 32.33. NOR gate, 34; RS
Flip-flop, 35; AND gate, 36; delay circuit

Claims (1)

[Claims] A display data RAM that stores codes of characters to be displayed in correspondence with display positions on a display screen, and a horizontal synchronization signal that provides a scanning address for sequentially reading data from the display data RAM in synchronization with a horizontal synchronization signal. a scan address generation circuit that generates and outputs the scan address based on the data; and a selector that normally supplies the scan address to the display data RAM and supplies the write address from the microcomputer to the display data RAM when write data is given from the microcomputer. , when write data is given from the microcomputer, the write signal from the microcomputer is latched, the latched write signal is given to the display data RAM during the horizontal retrace period, and the write signal is latched, and then writing is completed. a timing adjustment circuit that outputs a signal to the microcomputer to inhibit writing of the next data from the microcomputer; a character generator that generates a character pattern from the code read from the display data RAM; A character display device comprising: a display signal generation circuit that converts a character pattern output from the character generator into a display signal based on a horizontal synchronization signal.