JPH0327920B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a raster scanning type monitor equipped with a memory for storing data to be displayed, and particularly relates to a method for controlling the display of a monitor screen when updating data. Regarding the device that does it.

(Prior art) The conventional example is shown in Figures 2 to 4 in a non-interlaced manner.
This will be explained using figures.

In FIG. 2 showing the CRT monitor of the image processing device, 1 is an image memory that stores data to be displayed on the CRT 2, 3 is a memory that supplies horizontal and vertical synchronizing signals to the CRT 2, and a read address generator 4 that supplies horizontal and vertical synchronizing signals to the CRT 2. A synchronization signal generator 5 controls access to the image memory 1, a write address generator 6
7 is a write data generator that receives transfer data from an external memory, such as a disk device 8, and generates data to be written into the image memory 1; 7 is a D/A converter that converts digital data from the image memory 1 into analog data; be.

When data is transferred from the disk device 8 to the image memory 1 and displayed on the CRT 2, an operator first sets an address generation area in the write address generation section 5 via a CPU (not shown) or the like.
The write data generator 6 processes the transfer data from the disk device 8, supplies it to the image memory 1 as input data, and stores it in the address area set by the write address generator 5. The read address generator 4 generates a read address in synchronization with the read start signal generated by the synchronization signal generator 3. Data read out from the image memory 1 according to this address is converted into an analog signal by the D/A converter 7, supplied to the CRT 2, and displayed on the screen of the CRT 2 according to the vertical synchronization signal and the horizontal synchronization signal.

This timing operation is shown in FIG. Signal codes correspond to those in FIG. 2, d is a vertical synchronization signal,
b is a blanking signal for inactivating the D/A converter 7 (the blanking signal is also the retrace period of the CRT 2), f is a read address signal, e is a write address signal, and g is a write enable signal. Further, a is a readable signal including a horizontal synchronizing signal and a vertical synchronizing signal, and c is a horizontal synchronizing signal.

As shown in FIG. 4A, when the new image data "B" is transferred to where the old image "A" is displayed and the display screen is switched, in this prior art, a band-like image is first displayed at the top of the screen. A new image appears, and then, as time passes, the band-shaped area gradually expands downward, and is replaced by the new image "B" only after a predetermined time.

(Problem to be solved by the invention) By the way, the reason why the screen cannot be switched instantaneously is that the CRT screen has a predetermined number of scanning lines,
Since the display is constantly performed at a predetermined cycle, the writing operation to the image memory 1 is performed only during the period when no reading operation is being performed, so as not to cause disturbances in the display.
In other words, the blanking period (retrace period of CRT2,
That is, this is because it can only be performed on the "L" part in FIG. 3b, or the "H" part in FIG. 3g and e).

During the period when this readout operation is not being performed, on a normal CRT monitor, each frame is 44 to 45H.
(H is the horizontal period), and one frame is 1/60 seconds.
Since 525 scanning lines are sequentially scanned, the time per scanning line is 31.75 μs, so the time is approximately 44 to 45×31.75 μs≒1400 μs. Therefore, in order to write data to an image memory with a memory space of 512 x 480 display pixel lines (horizontal x vertical), the reading speed from disk 8 per pixel (writing speed to image memory 1) ) is 1μs, then 512×480/31.75μs×45/1μs×60≒2.9s. In other words, there is a problem that at least about 3 seconds of waiting time is required for all data transfer, that is, screen switching, which impedes the speed of processing operations, and moreover, data transfer from external memory, etc. is usually performed frequently. Therefore, it has become a heavy mental burden for the operator.

For this reason, attempts have been made to solve the above problems by erasing the screen display before starting processing or data transfer, and displaying the new data on the screen once the contents of the image memory have been rewritten. method was tried.

However, although it is true that switching the screen display is instantaneous (512 x 480 x 1 μs ≒ 0.25 s) and is perfect in terms of speed, with this method, a bright screen suddenly appears on a pitch black screen, which is difficult for the operator. I don't like it very much. That is, if this is repeated frequently, the operator will feel psychologically nervous, and it will also be unfavorable for the physiology of vision and the like.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a novel display control method that can speed up the display switching of a monitor screen and at the same time prevent the operator from feeling uncomfortable.

(Summary of the Invention) When switching the screen display, the present invention prohibits the reading of old data in the image memory, uses the read prohibition period to write new data, and reads and displays only this newly written data. The present invention is characterized in that access to the image memory is controlled so as to.

(Operation) As illustrated in FIG. 5, when switching the image "A" to the new image "B", first, the display of the image "A" as old data is completely erased. During this erasing period, part of the data of the new image "B" is written into the image memory, and then this written partial data is read out and displayed. Next, reading is prohibited from the part where the new image "B" is not written,
During that period, data for a new image "B" following the previous data is written, and the written data is read out and displayed in the next display period along with the data for the new image "B" that was written earlier. Ru. While the erased area corresponding to the read-inhibited period gradually shrinks, the display area expands as the erased area shrinks, and finally switches to the full screen "B". The time required for switching is within 0.7 seconds, as shown in the calculations below.

Therefore, the point in time when a new screen appears can be immediately detected, and the screen changes quickly, but the new screen is gradually enlarged and displayed, which adapts to the visual adaptation to light and dark, and does not give the operator a sense of discomfort. Less is.

(Example) The first example is a non-interlaced method.
As shown in the figure.

10 is a display control device for a CRT monitor.
The same reference numerals as in FIG. 2 indicate the same or equivalent parts.

The display control device 10 includes a down counter 11 that can be preset, an up counter 12 that can also be preset, a decoder 13 that decodes the output of the up counter 12, a NOR circuit 14 that receives the output of the decoder 13, and an inverter circuit. 1
5, 16, and 17. Note that the means for transferring the image data in the image memory 1 to the disk 8 is not illustrated because it is not an object of this invention.

When a CPU (not shown) performs control to start data transfer from the disk 8 to the image memory 1, the down counter 11 is simultaneously preset to a numerical value n by a preset signal from the CPU.
The numerical value n is a number equivalent to the number of scanning lines in one frame of the CRT monitor used here, in other words, the total number of scanning lines that can be displayed on the monitor screen, for example 480 (=
525-45). This down counter 11 is
Write address generator 5 writes to image memory 1
The pulse (i) outputted when the number of data equal to one scanning line of the CRT display (for example, 512) has been written is used as a clock to count down. Then, when its own output reaches φ, the counting operation is stopped by a borrow signal output. Note that the write address generation unit 5 holds the horizontal address (0 to 511) during writing for one scanning line during the read period.

The up counter 12 counts up in response to the horizontal synchronization signal c supplied from the synchronization signal generator 3. Further, the up-counter 12 uses the vertical synchronizing signal d inputted from the synchronizing signal generator 3 as a load signal, and presets the output of the down-counter 11 when the timing matches with the horizontal synchronizing signal c.

The decoder 13 decodes the output of the up counter 12, and outputs a high level signal "H" when the output of the up counter 12 is n. This "H" signal is inverted by the inverter circuit 15 and input to the enable terminal of the up counter 12, thereby stopping the up counter 12 from advancing. Therefore, when the up counter 12 reaches n, unless a preset signal is input, n
will be kept as is.

The two-input NOR circuit 14 receives at one input a signal obtained by inverting the conventional blanking signal b output from the synchronization signal generator 3 by an inverter circuit 16, and receives the output from the decoder 13 at the other input. . Only when both inputs are low level signals "L", the output h is set to "H" and the read address generating section 4 and the D/A converter 7 are activated. That is, when the count value of the up counter 12 is smaller than n and it is not the blanking period, the image memory 1
The stored data is displayed on the CRT2. When at least one of the two inputs is “H”, NOR circuit 1
4 outputs "L". That is, in addition to the conventional blanking period (signal b), a blanking period occurs when the output of the decoder 13 is "H".
Therefore, the signal h should be called a composite blanking signal. This composite blanking signal h
When , of course, the read address generator 4 and the D/A converter 7 are deactivated, but the write address generator 5 is activated via the inverter circuit 17, and writing to the image memory 1 is performed. It becomes possible. That is, writing is possible during the conventional blanking period and during the period when the up counter 12 reaches n and holds n.

To describe the series of operations when data is transferred to the image memory 1 and displayed on the CRT 2, when the operator inputs a command to transfer data from the disk device 8 to the image memory 1 and display it on the CRT 2,
The control section consisting of a CPU (not shown), etc.
The image area to be read from the disk is set, and the address area is set in the write address generating section 5, and a numerical value n is preset in the down counter 11. The up counter 12 loads the output data n of the down counter 11 when the vertical synchronization signal d and the horizontal synchronization signal c are inputted from the synchronization signal generation circuit 3. The output n of the up counter 11 is decoded by the decoder 13, and the output k of the decoder 13 becomes "H". This output is the NOR circuit 14
is applied to the D/A converter 7 as a composite blanking signal h, thereby erasing the entire display screen of the CRT 2. At the same time, the write enable signal g is set to "H" via the inverter circuit 17. During the period when the write address generation section 5 is activated and the image data from the disk 8 is at "H", the write enable signal g is "H".
It becomes writable. Along with this, the data transfer starts, and the value n of the down counter 11 does not change until data for one scanning line is written to the image memory 1, but the end signal i is input from the write address generation section 5. count down every time, n-1,
It changes as n-2, n-3,...

When the count value of the down counter 11 reaches n-k, the vertical synchronization signal d of the up counter 12
When input, n-k is set in the up counter 12. At the same time, the decoder 13 becomes "L" and the up counter 12 becomes incrementable. However, during the period when the vertical synchronization signal d of negative polarity is input, it does not step and is in a writable state. During this period, when one more scanning line data is written, the up counter 12 is set to a value of n-(k+l). The up counter 12 is n-
Stepping starts from (k+l). At this time, since the signal k is "L" and the signal b is "H", the NOR circuit 14 outputs "H", and both the read address generation section 4 and the D/A converter 7 are activated. From the image memory 1, a horizontal synchronization signal and a vertical synchronization signal are input from the synchronization signal generation section 3 to the read address generation section 4, and the rewritten data is sequentially read out.
Displayed on CRT2. The up counter 12 is
The count is increased by the horizontal synchronizing signal c, and while the up counter 12 is counting, the data written one frame before is displayed.

When the up counter 12 counts (k+l) (the CRT displays the rewritten scanning line data), the up counter 12 becomes the count value n. The decoder 13 detects this n, outputs "H", immediately stops the increment of the up counter 12 via the NOT circuit 15, and sets the signal h to "L" via the NOR circuit 14. This prohibits reading and also deactivates the D/A converter 7. In this way, the portions after (k+l) display scanning lines remain non-displayed.

The “L” level of the signal h causes the signal g to become “H” via the inverter circuit 17, thereby activating the write address generation unit 5. Therefore, data can be written during a period corresponding to this screen non-display area, and transfer data is subsequently written.
As described above, the down counter 11 is incremented every time one scanning line is written, and at the same time the up counter 12 is incremented every horizontal synchronization signal c.

FIG. 6 shows the timing when the count value of the down counter 11 reaches (n-m), that is, after m scanning line data have been written into the image memory 1. Further, in the figure, k means the number of lines written in the image memory during the non-display period during the "L" level of the vertical synchronization signal d. Note that in FIG. 6, the blanking signal b and the composite blanking signal h should originally include blanking components related to horizontal scanning, but for ease of understanding,
Only the vertical component is shown.

According to the above method, since reading from the image memory 1 is limited to the data update portion, the reading period can be shortened, and the data writable period can be lengthened by the shortened period. This can shorten the total data transfer time. The effects can be shown quantitatively as follows.

Assuming that the number of data for one scanning line corresponds to 512 pixels, writing is possible for the entire period in the first vertical period, so assuming the writing time per pixel is 1 μs, it is 31.75 μs × 525 / Finish writing 1μs×512≒32 (lines). Since only 32 lines are displayed in the next vertical period, writing is possible during the period of (525-32)H, and writing is completed in 31.75 μs x (525-32)/1 μs x 512≒30 (lines).

Generally, in the nth vertical cycle, the number of lines to be newly written is _ao , and _ao = 31.75/512 (525−a ₀ −a ₁ −a ₂ ...− _{a o-1} ), and _ao = ( 1-31.75/512) a _o-1 : a ₀ = 31.75/512×525≒3
2, and a _o = (1-31.75/512) ⁿ a ₀ is found.

Assuming that the number that can be written in the i-th vertical cycle is equal to the number that all data corresponding to the screen display is written to the image memory in the first vertical blanking period (45H), (1-31.75/ 512) ⁱ × 31.75 / 512 × 1 μs × 525 = 31.75 μs × 45 / 1 μs × 512 Therefore, i≒38, and approximately 38 including the first (a ₀ )
Only the period of the vertical cycle is required.

In terms of time, it is 1/60 (s) x 38≒0.64 (s),
In this time, screen data of 512 x 480 pixels can be written, which is an order that does not place a mental burden on the operator.

In the embodiments described above, a non-interlace method in which horizontal scanning is performed sequentially is used for display on a CRT. However, an interlace method can be used as well. That is, in the interlaced system, the output signal i from the write address generating section 5 of FIG. 1 in the above embodiment may be configured to be output when the number of data equal to two horizontal scans has been written. It is clear that the display can be carried out in the same manner as in the non-interlaced display, except that the relationship between the number of scanning lines of data written to the image memory 1 and the display period on the CRT is 2:1.

Furthermore, if the data writing order to the image memory 1 is set to be written sequentially in the vertical direction on the CRT 2 while the display order remains the same, the output signal i from the write address generation section 5 is divided by one pixel in the vertical scanning direction ( For example, 480) is output when writing is completed, and the initial setting value of the down counter 11 is set to 512, for example, and the clock c of the up counter 12 is inputted to a clock equal to one dot in the horizontal direction, thereby writing in the vertical direction. It can be easily inferred that it is possible to sequentially display only the contents of the loaded image memory 1 on the CRT. As for colors, it is sufficient to have a plurality of disk devices and operate them in parallel.

(Effects of the Invention) As described above, according to the present invention, only the rewritten data is displayed and the display of old data is prohibited, and the display prohibition period is used for writing updated data. The total transfer time can be shortened and screen displays can be switched quickly. Moreover, the screen display instantly displays part of the updated data immediately after the entire screen is blank, and the display area gradually expands like a converging geometric series, so it is difficult for visual adaptation to light and darkness. It is familiar to the operator and does not make the operator feel uncomfortable or fatigued.

Furthermore, the display control device of the present invention basically has a simple configuration using a down counter, an up counter, and ordinary logic elements, and there is no limit to the value n preset to the down counter. It can be applied regardless of the type of raster scanning monitor, that is, the number of display pixels (horizontal x vertical), and has the advantage of being highly versatile.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Fig. 2 is a block diagram showing a conventional example, Fig. 3 is a timing diagram of the conventional example, Figs. 4 A and B are explanatory diagrams of screen displays of the conventional example, and Fig. 5 is a screen according to an embodiment of the present invention. The explanatory diagram of the display, FIG. 6, is a timing diagram at a certain point in time of the circuit shown in FIG. 1... Image memory, 2... CRT, 3... Synchronization signal generation section, 4... Read address generation section, 5...
...Write address generator, 11... Down counter, 12... Up counter, 13... Decoder, 14... NOR circuit.

Claims (1)

[Scope of Claims] 1. In a raster scanning monitor equipped with a memory for storing data to be displayed, when data in the memory is rewritten, the entire screen is made blank, and then the non-display period of the screen is and controlling access to the memory so that data to be displayed during the blanking period of the monitor is stored in the memory, and newly stored data to be displayed is read from the memory to gradually expand the display area. A display control method for a monitor screen, characterized in that: 2 Equipped with a memory for storing data to be displayed,
In a device for controlling the screen display of a raster scanning monitor that performs screen display based on a synchronization signal from a built-in synchronization signal generator, when data in the memory is rewritten, the total number of scanning lines n of the monitor is preset. , a down counter that decrements by 1 each time data for one scanning line is written to the memory; and a count value of the down counter is preset based on a vertical synchronization signal supplied from the synchronization signal generation section; an up counter that is incremented by a horizontal synchronization signal supplied from a synchronization signal generator; a count value of this up counter is constantly detected; when the count value is smaller than n, reading from the memory is permitted; a memory access control unit that stops incrementing of the up counter and prohibits reading from the memory and at the same time allows writing to the memory when the up counter is incrementing; A display control device for a monitor screen, characterized in that only the rewritten data is read out and displayed, and the data is rewritten while an up counter is stopped incrementing.