JPS63108874A - Synchronizing method for picture processor - Google Patents

Abstract

PURPOSE:To directly take a synchronization according to a synchronizing signal extracted from an external video signal by presetting a counter for instructing horizontal and vertical positions to a preset value when an external synchronizing signal is supplied. CONSTITUTION:A picture processor 1 reads picture data (character code) in a VRAM3 under the control of a CPU2 and displays on a CRT display deice 5 based on the read data. the VRAM3 is suitably made access from the picture processor 1 or the CPU2 according to the switching processing of a multiplexer 4. A character generator 7 outputs dot data constituting a character pattern based on the character code supplied from the VRAM3 and a raster address RA supplied from the picture processor 1. In the picture processor 1, the counter for instructing the horizontal and vertical positions is disposed, and preset by the external synchronizing signal to decide the raster address.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a method of synchronizing an image processing apparatus, which is suitable for use in synchronizing display control by rask scan with an external signal.

"Prior Art" In an image processing device such as a CrtT controller, a horizontal counter that indicates a horizontal scanning position and a vertical counter that indicates a vertical scanning position are provided, and based on the count outputs of these counters, the display screen is Controls scanning.

"Problems to be Solved by the Invention" By the way, in an image processing device, display control is performed based on data in a VRAM (video RAM), and display control is performed based on data supplied from an external device. There is. Display based on external data may involve superimposing or digitizing, but in such cases, it is necessary to perform processing in synchronization with the external video signal.

In this case, in conventional image processing devices (for example, Motorola's MC6845, etc.), the horizontal and vertical counters are configured to be reset by an external signal. It was not possible to set the counter directly using a signal.

This is because the reset state of the horizontal and vertical counters indicates the start point of display, and if the counters are reset with an external synchronization signal, the display timing will be lost.

For example, horizontal display is performed after a predetermined time has elapsed after the horizontal synchronization signal is output, but if the horizontal counter is reset by an external horizontal synchronization signal, the timing at which display should start will be earlier than the normal timing. This is the translation. This also applies to vertical display.

Therefore, in conventional image processing devices, it is not possible to directly synchronize from an external synchronization signal, and therefore a synchronization signal for resetting the horizontal and vertical counters must be created separately based on the external synchronization signal. However, the disadvantage is that the circuit configuration becomes complicated.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a synchronization method for an image processing apparatus that can directly synchronize using a synchronization signal extracted from an external video signal.

"Means for Solving the Problems" In order to solve the above problems, the present invention has a horizontal counter that indicates a horizontal scanning position and a vertical counter that indicates a vertical scanning position, and the counters of these counters. An image processing device that controls the display position of dots based on a count output is characterized in that the horizontal and vertical counters are preset to predetermined values when an external synchronization signal is supplied.

, "Effect" The predetermined values can be set so that the contents of the horizontal, vertical, and counters become "0" when the raster reaches the display start position, thereby synchronizing directly with an external synchronization signal. be able to.

"Embodiments" Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Configuration of Embodiment) FIG. 2 is a block diagram showing the overall configuration of an image processing apparatus to which an embodiment of the present invention is applied. Note that this embodiment is an example in which the present invention is applied to a character display device.

In FIG. 2, reference numeral 1 denotes an image processing device, which reads image data (character code in this case) in VRAMa under the control of the CPU 2, and displays it on the CR7 display device 5 based on this successive data. The VRAM 3 is configured to be accessed from either the image processing device 1 or the CPU 2 as appropriate through switching processing of the multiplexer 4. 7 is a character generator,
Based on the character code supplied from VRAM3 and the raster address RA supplied from image processing device l,
Outputs dot data that makes up a character pattern.

Here, the raster address RA will be explained.

Now, as shown in Figure 3, if eight rasters are used to display one line (including the line spacing), the numbers indicating the O to 7 rasters shown in the figure are the raster addresses. Become. In this case, assuming that the number of dots in the vertical direction of the character pattern is 6 as shown, the raster addresses indicating the sixth and seventh rasks are unnecessary for the character generator, and only the rasters are displayed.

Next, 8 shown in FIG. 2 is a parallel/serial converter, and the pattern data converted into serial data here is supplied to the video control circuit 9. The video control circuit 9 transfers the supplied serial pattern data to the image processing device! Control signals (synchronization signals and dot clock pulses, etc.) supplied from
is displayed on the CR7 display device 5 based on.

Next, the configuration of the main parts of this embodiment will be explained with reference to FIG. The circuit shown in FIG. 1 is a circuit provided in the image processing apparatus l, and in the figure, 15 is
This is a start address register into which the access start address for IAM3 is written by CPU2. The output data of the start address register 15 is supplied to the input terminal B of the selector 16, and the output data of the selector 16 is supplied to the preset data input terminal PD of the counter 17. This selector 16 selects the input terminal B when the "1" signal is supplied to the terminal SB, and selects the input terminal A when the "0" signal is supplied to the terminal SB. A clock pulse CLK (its period corresponds to the display period of one character) is supplied to the clock input terminal of the counter 17 via an AND gate ANI. In this case, the AND gate ANl is in an open state when the signal HDE is a "1" signal, and this signal HDE is controlled to be a "1" signal during the horizontal display period, as will be described later.

The count output of the counter 17 is supplied to the address input terminal of the VRAM 3 as memory address data MA, and is also supplied to the input terminal of the register 19. This register 19 is a register that latches the count output of the counter 17 when a "1" signal is supplied to the terminal "L", and its output data is supplied to the input terminal A of the selector 16. .

22 is a horizontal total character number register in which the total number of characters in the horizontal direction on the display screen, that is, the sum of the number of characters displayed on the screen plus the number of characters corresponding to the horizontal retrace period, is written by the CPU 2. That is, the value written to the horizontal total character count register corresponds to one rask period (horizontal scanning period). A character counter 24 counts the clock CLK corresponding to the display time of one character. The output data of the character counter 24 and the horizontal total number of characters register 22 are arranged so that a digital comparator 23 detects whether their values match. The digital comparator 23 is
When a match of two data is detected, the output signal HMAX is set to “l”.
” signal. This signal HMAX is supplied to the character counter 24 as a reset signal.
The signal HMAX is reset at the next rising edge of the clock signal CLK after the clock signal CLK becomes ``.In other words, the signal HMAX is output for a period corresponding to the display period of 1 character at the end timing of horizontal scanning. HMAX is supplied to each one input terminal of AND gate AN2.3 and the set terminal of flip-flop 40 as shown.

45 is a horizontal synchronization position register into which data is written by the CPU 2, and the count value of the corresponding character counter 43 is written when the horizontal synchronization signal is output.

The contents of the horizontal synchronization position register 45 are loaded into the character counter 24 when the external horizontal synchronization signal H8YNC is supplied to the preset terminal PS of the character counter 24. Although not shown, during a predetermined count after the count value of the character counter 24 matches the content of the horizontal synchronization position register 45,
An internal horizontal synchronization signal is output to the video control circuit 9.

25 is a one-line raster number register in which the number of rasters corresponding to one line on the display (including the raster of the inter-line pitch) is set by the CPU 2, and 26 is the number of rasters displayed on the screen by counting the signal HMA This is a raster counter that counts the number of rasters. In this case, the output of the raster counter 26 is output to the character generator 7 as a raster address RA. Furthermore, the output data of the one-row raster number register 25 and the count output of the raster counter 26 are transferred to the digital comparator 27.
The coincidence is detected by the above, and the output signal REQ is configured to become an "I" signal when there is a coincidence. This signal REQ is supplied to the raster counter 26 as a reset signal, so that the raster counter 26 receives the next signal HM after the signal REQ becomes "L".
It is configured to be reset at the rising edge of AX. That is, the signal REQ becomes "1" while the final raster of each row is being scanned, and is reset at the end of the final raster.

This signal r(EQ is supplied to the other input terminal of the AND gate AN2 via the inverter INVI, and
It is supplied to the input terminal of AND gate AN3. The output signal of the AND gate AN2 is the preset terminal P of the counter 17.
At S, the output signal of the AND gate AN3 is supplied to the load terminal of the register 19 and the reset terminal R of the flip-flop 35.

30 is a total line register in which the total number of lines per frame including vertical retrace time is set by the CPU 2; if the total number of lines is N, (N-1
) is written. 31 is a line counter that counts the number of displayed lines (rows) by counting the signal REQ. This line counter 26 is configured to take in data in the vertical synchronization position register 46 as a preset value when an external vertical synchronization signal VSYNC is supplied. A count value corresponding to the output timing of the vertical synchronization signal is written into the vertical synchronization position register 46 by the CPU 2.

Although not shown, a flip-flop is provided that outputs an "L" signal during a predetermined count after the count value of the line counter 31 matches the contents of the vertical synchronization position register 46, and the output of this flip-flop is is used as an internal vertical synchronization signal.

The output data of the total line register 30 and the count output of the line counter 31 are transmitted to the frame end detection section 3.
2. The frame end detection unit 32 detects the end of one frame based on the output signals of the total line register 30, the digital comparator 27, and the line counter 31, and the number of corrected rasters in the vertical retrace period, and detects the end of the last raster. At the timing of scanning, the output signal VT is set to an "L" signal. This signal VT is supplied to the set terminal S of the flip-flop 35, and is also supplied to the line counter 3I as a reset signal. The line counter 31 is reset each time the signal VT becomes a "1" signal at the end of one frame.

Next, 42 is a horizontal display character number register, into which data indicating the number of horizontal display characters is written by the CPU 2. ◇Horizontal display character number register 4
2 and the count output of the character counter 24 are adapted to be detected by a digital comparator 43, and the output signal of the digital comparator 43 is supplied to the reset terminal of the flip-flop 40. ing. The output signal of the flip-flop 40 becomes an "l" signal after the signal HM A X becomes an "l" signal until the digital comparator 43 becomes an "l" signal. That is, the signal becomes "l" during the horizontal display period.

Further, 41 is a flip-flop whose set terminal is supplied with the signal VT and whose reset terminal is supplied with the signal LEQ. The signal LEQ is an output signal of the digital comparator 48, and becomes an "1" signal when the count output of the line counter 31 and the contents of the vertical display character number register 47 match. Data instructing the number of vertically displayed characters is written into this vertically displayed character number register 47 from the CPU 2. With the above configuration, the output signal of the flip-flop 41 indicates that the content of the line counter 31 is 0.
The signal becomes "1" during the period from 1 to the number of vertically displayed characters. That is, it becomes an "L" signal during the vertical display period.

The respective output signals of the flip-flops 40 and 41 are ANDed by an AND gate AN5, and this AND signal is supplied to the input terminal of the AND gate ANI as the signal I DE described above. Since the signal HDE is the logical product of the horizontal display period and the horizontal display period, it becomes an "l" signal in the horizontal display period that does not include the retrace period.

As can be seen from the above configuration, when the display of the next frame ends and the display of the next frame starts, the count values of the line counter 31 and the character counter 24 change to "
0". In other words, if these counters are “0”
” value indicates the display start timing.

Therefore, the values of the horizontal synchronization position register 45 and the vertical synchronization position register 46 are the count values corresponding to the end points of the horizontal and vertical display periods, respectively (i.e., the horizontal display character number register 42 and the vertical display character number register 47).
value) is set to a larger value.

Furthermore, in the above circuit, the entire circuit can be reset, and upon resetting, the contents of the character counter 24, raster counter 26, and line counter 31 are cleared.

(Operation of Example) Next, the operation of this example with the above configuration will be explained.

First, as an example, assume that 40 characters x 16 lines are to be displayed, and Adxl is set as the start address, and 8 lines are set as the number of rasters per line. In this case, the CPU 2 writes address data (Adxl) to the start address register 15, and then writes “3” to the horizontal display character number register 42.
9”, “7” is written in the one-line raster number register 25, and “15” is written in the vertical display character number register 47. Furthermore, Yll is stored in the vertical synchronization position register 46, yt (y*>yt) is stored in the total line register 30, and horizontal synchronization position register 4
5, xl, and horizontal total character count register 22, X.

Write (X * > X +).

First, the operation when no external synchronization signal is used will be explained.

When the circuit is driven from the reset state, the character counter 24 starts counting the clock CLK having a period equal to the display timing of one character. The count value of this character counter 24 is the horizontal synchronization position register 4.
When the count matches the value X1 within 5, a horizontal synchronizing signal is output from the time of the match until a predetermined count is reached. When the count value of the character counter 24 matches the value X in the horizontal total character count register 22, the signal HMAX becomes an "l" signal, and the raster counter 26
performs an up count. Thereafter, when the above operation is repeated and the last raster of the row is counted by the raster counter 26, the contents of the one-row raster number register 25 and the count value of the raster counter 26 match, and as a result, the output of the digital comparator 27 The signal REQ becomes an "L" signal, and the line counter 31 performs up-counting. From then on, the count value of the line counter 31 is incremented every time the signal rlEQ becomes "L".
This count value and the value Y1 in the vertical synchronization position register 46
If they match, a vertical synchronizing signal is output during a predetermined number of further counts from this point. Then, when the count value of the line counter 31 matches the value Y in the total line register 30, and the scanning progresses further and the scanning of the number of corrected rasters in the vertical blanking period is completed, the frame end detection unit 32 detects the frame end. Detects the end of the signal VT and sets the signal VT to an "L" signal.

When the signal VT becomes a “!” signal, the flip-flop 35
is set, the selector 16 selects the input terminal B, and the flip-flop 41 is set. Further, at the time when the signal VT becomes "I", the raster counter 26 and the line counter 31 are cleared. Also,
When the last raster has been scanned, the value X in the horizontal total character count register 22 and the character counter 24 are
matches the value of , the signal HMAX becomes an "l" signal, the character counter 24 is reset, and
Flip-flop 40 is set. In this way, at the end of the frame when the signal VT becomes the "L" signal,
The line counter 31, raster counter 26, and character counter 24 are each cleared, and the flip-flops 35°40.41 are set all at once. Also, just before the scanning of the final raster of one frame ends, the signal REQ is "0" and the signal HM A X is "l".
As a result, the counter 17 performs a preset operation. At this time, the start address data in the start address 15 is preset because the selector 16 has selected the input end B. In the above operation, the AND gate AN5 is in the closed state before VT becomes "L", so the signal 1-IDE becomes "
1'', the counter 17 does not count up, and the memory address MA is not incremented.

Now, by the above operation, the flip-flop 40.41
When IDE is set, the output signal IDE of the AND gate AN5 becomes the "L" signal, thereby starting display, and the clock CLK is supplied to the counter 17 via the AND gate ANI, and the memory address MA
is incremented. That is, counter I7
The count output is sequentially incremented by 1 from the start address Adxl in synchronization with the clock pulse CLK. As a result, the character codes of the characters to be displayed in each display section are sequentially outputted from the VRAM 3, and the corresponding character patterns are read out from the character generator 7.

Since the character pattern read at this time has the raster address "0", it is pattern data corresponding to the raster address "0" (see FIG. 3). Then, the raster address read from the character generator 7 is
0'' pattern data is sent to the parallel/serial converter 8.
After being converted into serial data, the data is supplied to the video control circuit 9, whereupon it is displayed on the CRT display device 5 based on the dot clock pulse.

By doing the above, the raster address in the 0th line "
0" is displayed. When the count value of the character counter 24 matches the value in the horizontal display character number register 42, the flip-flop 40 is reset, and as a result, the signal HDE falls to "0", display is prohibited, and the counter 17 is Counting operation is stopped.

Next, the counter of the character counter 24 advances to x
When it reaches "l", a horizontal synchronizing signal (horizontal synchronizing signal for the next raster scan) is output, and when it reaches X, the signal HMAX becomes "l" and the character counter 24
is reset, and the flip-flop 40 is reset again.
is set and display starts. Furthermore, at the end of scanning raster address "0", REQ is "0", ! -1M
Since AX becomes "l", the counter 17 performs a preset operation. At this time, since the selector 16 has selected input end B, the start address A is preset.
It is dxl. Then, when the signal HD E h <"l" signal and the horizontal display period begins, the same display operation as above is performed, but at this point, the raster counter 2
Since 6 has been incremented by 1, the pattern data at raster address rlJ is displayed. Thereafter, raster addresses r2J, r3J, . . . are sequentially displayed. Then, when the display of raster address "7" is finished and just before the end of scanning of this raster, both signal REQ and signal HMAX become "l" signal, and as a result, AND gate AN3 outputs "l" signal Output.

When the AND gate AN3 outputs the "L" signal, the register 19 performs a loading operation even though the flip-flop 35 is reset. At this time, the selector 18 has selected the input terminal A, so the register 19 is set at the end of the display period of the raster address "7" (signal IDE is "0").
Loads the value of memory address MA at the time the signal is generated.

Then, when the next scan is started and the horizontal display period for the raster address "0" in the first row begins, the signal IIDE rises to the "summer" signal, and the AND gate ANI becomes open, and as a result, the counter 17 Start counting up. In this case, since the counter 17 is not performing a preset operation, the data is sequentially read to the VRAM 3 from the address next to the last successive address of the previous row, and the read data causes the same display as in the above case. Processing continues. At the end of displaying the raster address "0" in the first row, the signal REQ becomes "0", the signal HMAX becomes "1", and the counter 17 performs a presetting operation. At this time, since the selector 16 has selected the input terminal A, the value preset in the counter 17 is
This is the data in the register 19, that is, the value of the counter 17 when the signal IDE falls to "0" in scanning the 0th row.Therefore, the next raster, the raster address address "1". ”, the counter 17 is incremented sequentially from the data in the register 19, but in the end the counter 17 is incremented by the raster address “0” in the first row.
is incremented from the same value as in the case of ``.

As described above, scanning of the first row and data reading are performed. Then, before the second line is displayed, the initial count value of the counter 17 is updated again, and thereby consecutive addresses in the VRAM 3 are sequentially accessed.

As described above, the display of each line progresses in sequence, and the display of the 15th line, which is the final line, is completed, and then the line counter 3
When the count value of 1 matches the content of the vertical synchronization position register 46, a vertical synchronization signal for the next frame is output from the time of the match until a predetermined count is reached.

Then, when the count value of the line counter 31 advances and matches the contents of the total line register 30, and furthermore, when the scanning of the correction raster during the vertical retrace period is completed, the frame end detection section 32 detects the display of a frame, and the signal V
T rises to “L” signal. As a result, the flip-flop 35 is set, the selector 16 selects the input terminal B, and supplies the start address Adxl to the preset data input terminal PD of the counter 17 again. Then, at the end of the final raster, the signal REQ becomes "0", the signal 11MAX/+("1"), the analogue AN2 outputs the "1" signal, and the counter 17 performs a presetting operation. As a result, from the start of display of the next frame, the count output of the counter 17 is changed to the start address Ad.
It is sequentially incremented from xl.

, Thereafter, the above-described operations are repeated, and thereby characters are displayed on the display screen based on the data in VI'lAMa.

Next, a case in which display processing is performed using an external synchronization signal will be described. When an external synchronization signal is used, the processing is basically the same as that described above, but the operations of the character counter 24 and line counter 31 are different.

The operation of the line counter 31 will be described below as an example. Now, the external synchronization signal VSYNC is at time 1.0 as shown in FIG. 4(a). At this point, the line counter 31 performs a presetting operation and presets the data Y1 in the vertical synchronization position register 46 as shown in FIG. 4(c). As a result, while the line counter 31 is counting a predetermined value from time t1, the internal vertical synchronization signal is output, and the video control circuit 9
(See Figure 2). That is, the internal vertical synchronization signal is output at the same timing as the external vertical synchronization signal. Further, when the count of the line counter 31 advances and matches the value Y in the total line register 30, the end of the frame is detected after the correction last scan from this point on, and the signal ■T becomes a "1" signal, and the fourth The line counter 31 is reset as shown at time t in the figure. That is, from this point on, the vertical display period starts as shown in FIG. 4(b). Thereafter, a similar operation is performed every time the external vertical synchronization signal VSYNC is supplied (see time t in FIG. 4).

According to the above operation, the internal vertical synchronization signal is output at the timing when the external vertical synchronization signal ■5YNC is supplied, and the count of the line counter 31 is the interval between the time when the external synchronization signal is supplied and the display start time. Since it is controlled by the interval from Yl to Yt, the timing from the generation of the vertical synchronizing signal to the start of display matches the preset timing.

On the other hand, if the counter is reset by an external signal as in the conventional counter reset method, the timing of the vertical display period will be shifted, as shown in Figure 4 (D) and (E), resulting in proper display processing. can't do it.

The above has described the operation of the vertical synchronization signal and the line counter 31, but the operation of the character counter 24 with respect to the external horizontal synchronization signal is also similar. That is, the waveform shown in Figure 4 (A) is used as the external horizontal synchronization signal, and the waveform shown in Figure 4 (C) is used as the external horizontal synchronization signal.
If the count value of is replaced with the count value of the character counter, a diagram showing the timing of each part in this case will be obtained.

Although the above embodiment is an example in which the present invention is applied to a character display, the present invention can of course also be applied to a graphic display.

"Effects of the Invention" As explained above, according to the present invention, there is provided a horizontal counter that indicates the horizontal scanning position and a vertical counter that indicates the vertical scanning position, and the dot count is calculated based on the count outputs of these counters. In the image processing device that controls the display position of the image processing apparatus, the horizontal and vertical counters are preset to predetermined values when an external synchronization signal is supplied, so that direct synchronization can be achieved using the external synchronization signal. This makes it possible to simplify control and circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the main parts of an image processing device that is an embodiment of the present invention, FIG. 2 is a block diagram showing the overall configuration of the same embodiment, and FIG. FIG. 4, a diagram showing the relationship, is a waveform diagram of each part of the circuit for explaining the operation of the same embodiment. 3...VRAM, 16.18...Selector, 17...Counter, 24...Character counter (horizontal counter), 3"...・
Line counter (vertical counter).

Claims (1)

[Claims] An image processing device that has a horizontal counter that indicates a horizontal scanning position and a vertical counter that indicates a vertical scanning position, and that controls a dot display position based on count outputs of these counters, wherein the horizontal and vertical counters are ,
1. A method for synchronizing an image processing apparatus, characterized in that a preset value is preset when an external synchronization signal is supplied.