JP2901658B2 - Display controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display controller for reading image data to be displayed from a memory and supplying the image data to a dot matrix display.

(Prior art)

Conventionally, a display device of a dot display system generally turns on a display pixel of a display panel 3 whose position is designated by an X driver 1 and a Y driver 2 in accordance with image data as shown in FIG. Display in form.

As described above, a commercially available driver for designating the display position of the display panel and lighting and driving the display pixel at that position has a predetermined number of drivable dots of, for example, 64, 80, and 100. Therefore, when forming a display screen of 128 dots (X direction) × 16 dots (Y direction),
As the X driver, a driver of 64 dots and two drivers of 80 dots are used. An 80-dot driver is used as the Y driver.

Since a large number of drivers need to be used depending on the dot configuration of the display screen as described above, the display screen is divided as shown in FIG. 8 and dot information display scanning is performed for each divided screen to reduce the number of drivers. It has been proposed to. In this proposal, as shown in FIG. 9, a display screen of 128 dots (X direction) × 16 dots (Y direction) is divided into two, and the driving of the driver is 64 dots (X direction) × 32 dots (Y Direction)). For this reason, the X driver can drive a display screen of 128 dots × 16 dots with only one 80 dot commercially available driver.

[Problems to be Solved by the Invention] However, in this type of conventional display device, since the display screen is displayed and scanned for each divided screen as described above, the display order of dots is constant for each screen. When the screen shifts to the next split screen, in the example of FIG. 8, when the display of the first split screen ends and shifts to the second screen, the display order changes.

For this reason, it has become necessary to read out the dot image data to be displayed from the memory that stores the dot image data in accordance with the display order described above. Therefore, when reading the image data from the memory,
A central processing unit (CPU) capable of variably setting a read address is used. There is a limit to the image reading speed of the central processing unit. I had to.

Instead of the central processing unit, a high-speed display controller (also called a direct memory access (DMA) controller) may be used, but the conventional display controller randomly sets the memory read address variably. Therefore, there is a problem to be solved in that image data cannot be read out corresponding to the above-described divided display screen.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a controller for a display which can solve such a problem and can read out image data from a memory for each divided display screen.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a display screen with a first region and a second region, such that one scanning line on the display screen is a plurality of scanning lines. A display controller that reads the image data from a memory in order to supply the display target image data to a display that performs display scanning for each of the divided display screens. First address generation means and second address generation means for generating an address signal designating an address for the first area and the second area, respectively, the first address generation means and the second address generation First and second initial value setting means for setting respective initial values of the means, and an address generated by the first and second address generating means. Address selection means for selectively inputting the address signal to the memory;
When an address signal designating a read address of the last scanning line in the first area is generated by the first address generating means, the first address generating means controls the second address generating means from the first address generating means. When an address signal designating the address of the last scanning line in the second area is generated by the second address generating means, the address is selected so as to select the first address generating means from the second address generating means. Control means for controlling the selection means.

[Operation] In the present invention, the next area is scanned after the last line of the divided area is scanned. Thereby, in the present invention,
A configuration that reduces the number of drivers for scanning can be adopted,
An address optimal for this configuration can be generated.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, an example of a system configuration of a display device to which the present invention is applied will be described with reference to the block diagram of FIG.

In FIG. 2, a CPU 300 receives image data to be displayed from an external device, and a random access memory (RAM) 200
Is stored in association with the display position. Further, the CPU 300 transmits various setting information described later to the display controller 100 before displaying the image data.

The image data is read from the display controller 100 RAM 200 in accordance with a predetermined display order, and the read image data is transferred to the display 400.

The display 400 comprises an X driver 1, a Y driver 2 and a display panel as in the conventional example shown in FIG. The display panel 3 has a display screen of 128 × 16 dots, and the display screen defines display addresses “0000” to 00FF (hexadecimal) along the horizontal direction. FIG. 3 shows the memory addresses of the RAM 200 for storing data.

In FIG. 3, the 8-bit image data of the display address “0000” is a digit address “0” and a row address “0” of the RAM 200.
Is stored in Hereinafter, the image data is stored in the form of a matrix (table) so that the display position and the storage position correspond to each other.

In this embodiment, as shown in FIG. 8, a first divided screen of display addresses "0000" to "007F" (hexadecimal) and a second divided screen of display addresses "0080" to "00FF" (hexadecimal) are used. Are displayed alternately.

Next, a circuit configuration of the display controller 100 according to the present invention is shown in FIG.

In FIG. 1, reference numeral 101 denotes a first display start address setting register, and an address value “00,0” of the RAM 20 corresponding to the first display position “0000H” of the first divided screen (see FIG. 3).
Stores 0 "(decimal number).

Reference numeral 102 denotes a first digit address counter,
Using the address value stored in the display start address setting register 101 as an initial value, sequentially from “00” → “01” → “02”
.... First split screen like "07" (see Fig. 3)
Generates a digit address in the horizontal line direction.

Reference numeral 103 denotes a second display start address setting register, which is the first display position (“00”) of the second divided screen (see FIG. 3).
80H ") and the corresponding address value" 00,08 "(decimal number) of the RAM 20. The upper two digits of the address value indicate the row address, and the lower two digits indicate the digit address.

104 is a second digit address counter, and the second digit address counter of RAM 200
The address values stored in the display start address setting register 103 are sequentially set as initial values from “08” to “09” in order.
A digit address in the horizontal line direction of the second divided screen (see FIG. 3) is generated as "15".

Reference numeral 105 denotes a display character number setting register which stores the number of characters constituting one horizontal line of each divided screen. In this example, "8" is stored. The read address is the same number of times as the stored value of the display character setting register 105, that is, the read address is equal to the first and second digit address counters 102 and 10 for the image data read number of one line.
4, the first and second digit address counters 102, 104 are automatically reset to the first and second digit address counters.
The counting is started from the initial value indicated by the display start address setting registers 101 and 103.

The display start address registers 101 and 103 and the address counters 102 and 104 operate as a plurality of address generating means. Reference numeral 109 denotes a multiplexer, based on a switching signal from the comparison circuit 107, for the first and second digit address counters 10.
Select and output 1,103 output addresses. The multiplexer 109 operates as an address selection unit.

Reference numeral 106 denotes a display line number setting register, which stores the number of horizontal lines constituting the divided screen.

A row address counter 108 counts the number of horizontal line scans by counting clock signals generated by the pulse generator 110.

107 detects the end of the display scan of each divided screen by comparing the count value of the row address counter 108 with the value stored in the display line number setting register 106, and
Is instructed to switch the address signal.

Reference numeral 110 denotes a pulse generator circuit, which generates a synchronization signal for counting the counters 102, 104, and 108 in synchronization with the display scan of the display with respect to the counters 102, 104, and 108. The pulse generator circuit 110 includes a shift clock pulse SCP and a latch pulse L for driving the display 400.
Various synchronization signals such as P, frame pulse FR and RAM200
Also generates a read signal.

A parallel-serial conversion circuit 111 converts 8-bit parallel image data output from the RAM 200 into a serial image signal.

Reference numeral 112 denotes a display control circuit, which performs image processing such as blinking (flickering), black / white inversion, and non-display of an image.

Since the pulse generator circuit 110, the parallel-serial conversion circuit 111, and the display control circuit 112 can be used in the same manner as in the conventional example, only a brief description will be given.

The operation of such a circuit will now be described with reference to FIGS.

FIG. 4 shows a control procedure executed by the CPU 300 of FIG.
FIG. 5 shows the contents of the address signal input to the RAM 200 of FIG.

In FIG. 4, a CPU 300 (see FIG. 2) receives predetermined values of the above-described registers 101, 103, 105, and 106 from an external device prior to a display operation, and registers the registers 101, 103, and
Write to 105 and 106 (steps S1 and S2).

When the display operation is started, a process (steps S3 and S4) of synchronizing with the display controller 100 and writing the display target screen data received from the external device into the RAM 200 in association with the display position is repeatedly executed.

On the other hand, in the display controller 100 (refer to the first example), the first and second digit address counters 101 and 103 count the clock signals generated by the pulse generator 110, and thereby the digit positions for the first divided screen and the second divided screen, respectively. Generates a read address.

The multiplexer 109 selects the output value of the first digit address counter at the time of starting. The digit address output from the multiplexer 109 and the row address output from the row address counter 108 are input to the RAM 200 as read addresses for the first split screen.

As shown in Fig. 5, (0,0) → (0,1) → (0,2) →
The read addresses of the first row of the first divided screen are sequentially generated in the order of (0, 3). The RAM 200 outputs the 8-bit image data stored in the corresponding address according to the read address and the read signal transmitted from the pulse generator circuit 110.

This image data is supplied to the display 400 via the parallel-serial conversion circuit 111 and the display control circuit 112. As a result, the image data from the RAM 200 is sequentially displayed on the display screen of the display 400 on the first divided screen as shown in FIG.

When the number of read addresses for one line of the first divided screen is generated, the first digit address counter 102 is automatically reset and starts counting again from the initial value "00". The second digit address counter 104 is also automatically reset. On the other hand, since the count value of the row address counter 108 is updated from “0” to “1”, the read address of the RAM 200 is divided into (1, 0) → (1, 1). The storage address of the image data on the second line of the screen is designated.
When such a processing procedure is repeated and the display scan of the first divided screen is completed, the comparison circuit 107 detects that the count value of the row address counter 108 has reached the number of display lines, and the comparison circuit 107 switches the switching signal. Occurs. Therefore, the multiplexer 109 selects and outputs the output address of the second digit address counter 104 next.

As a result, the read address for the RAM 200 is switched for the second split screen, and (0,8) → (0,9) → (0,10).
・ ・ It is set as follows. Hereinafter, the second digit address counter 104 and the row address counter 108 are processed by the same processing as the above-described processing of generating the read address for the first divided screen.
Generates a read address.

Hereinafter, when the final read address of the second divided screen is generated, the multiplexer 1
09 selects and outputs the output address of the first digit address counter 102.

Thus, the display screen of the display 400 (see FIG. 8)
In the above, the image display of the first split screen and the image display of the second split screen are performed alternately.

As described above, in this embodiment, the address counter 10
Since the read address of the RAM 200 is created by 2,104,108, it is not necessary to correspond to the processing speed of the CPU 200. Further, since the CPU 200 only has to perform the process of writing the image information to the RAM 200, the software can be shortened and the processing load can be reduced as compared with the related art.

Further, by setting the display start address of each divided screen and the number of characters to be displayed on one horizontal line variably by the CPU 200, it is also possible to specify the window of the readout area of each divided screen.

The following examples are conceivable in addition to the embodiment of the present invention. That is,
In the embodiment of the present invention, display scanning is performed in the horizontal direction for each divided screen as shown in FIG. 8, but the display scanning direction may be vertical as shown in FIG. 6 (A). .
In this case, the display controller in the circuit shown in FIG.
The circuit configuration is such that rows are replaced by digits and digits are replaced by rows.

Further, as shown in FIG. 6 (A), it is also possible to switch the divided screen to be scanned each time display scanning of one line is completed. In this case, the address counter may be switched for each line.

FIG. 6B shows the connection configuration of the driver of the display 400 and the display address arrangement in the display scan order shown in FIG. 6A for reference, and the image data corresponding to the display address for the RAM 200 is shown in FIG. Are shown in FIG. 6 (C).

[Effects of the Invention] As described above, according to the present invention, the next area is scanned after the last line of the divided area is scanned. As a result, in the present invention, it is possible to adopt a configuration in which the number of scanning drivers is reduced, and it is possible to generate an optimum address for this configuration.

[Brief description of the drawings]

1 is a block diagram showing a circuit configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a system configuration of a display device to which the present invention is applied, and FIG. 3 is an address configuration of a RAM 200 shown in FIG. FIG. 4 is a flowchart showing a control procedure executed by the CPU 300 shown in FIG. 2, FIG. 5 is a timing chart showing contents of read addresses in the embodiment of the present invention, and FIG. FIG. 6B is a plan view showing a connection example of a driver according to a second embodiment of the present invention, and FIG. 6C is a readout of the second embodiment of the present invention. FIGS. 7 and 9 are timing charts showing the contents of addresses, FIGS. 7 and 9 are plan views showing examples of connection of a conventional driver, and FIG. 8 is an explanatory view showing a display scanning order of the conventional example. 1,2 ... Driver, 3 ... Display panel, 100 ... Display controller, 101,103 ... Display start address setting register, 102,104 ... Address counter, 109 ... Multiplexer, 200 ... RAM, 300 ... CPU, 400 ... Display.

Claims (2)

(57) [Claims] 1. A display for dividing a display screen into a first area and a second area so that one scanning line on the display screen becomes a plurality of scanning lines, and performing display scanning for each of the divided display screens. A display controller for reading image data from a memory in order to supply image data to be displayed to a display, wherein an address signal designating a read address of the memory is provided for the first area and the second area. First address generating means and second address generating means which are respectively generated; first initial value setting means for setting respective initial values of the first address generating means and the second address generating means; and 2 initial value setting means, and address selecting means for selectively inputting the address signal generated by the first address generating means and the second address generating means to the memory. When an address signal designating a read address of the last scanning line in the first area is generated by the first address generating means, the first address generating means controls the second address generating means from the first address generating means. When an address signal designating the address of the last scanning line in the second area is generated by the second address generating means, the address is selected so as to select the first address generating means from the second address generating means. A controller for a display, comprising: control means for controlling a selection means. 2. The apparatus according to claim 1, wherein said first address generating means and said second address generating means can variably set a designated range of said read address to an externally designated range. Display controller as described.