JPS63124084A - Character display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a character display device, and in particular, to
The present invention relates to a character display device in which data is written in synchronization with a horizontal synchronization signal in order to prevent flickering when data is rewritten to AM on an effective screen.

[Conventional technology]

In the conventional character display device of this kind, as shown in the block diagram of FIG. 3, writing from a microcomputer (hereinafter referred to as microcomputer) 18 to the display data RAM 21 was always performed in synchronization with a horizontal synchronizing signal. .

[Problem that the invention seeks to solve]

The conventional character display device described above uses display data RA
Since data is always written to M in synchronization with the horizontal synchronization signal, when completely synchronized horizontal and vertical synchronization signals are input to this character display device, the vertical blanking line is There is no horizontal synchronization signal during the period, and during the vertical retrace period, the display data RAM is sent from the microcomputer.
The disadvantage is that you cannot write to it at all.

An object of the present invention is to enable character display that allows writing from a microcontroller to display data RAM even during a vertical retrace period when no horizontal synchronizing signal is input, and that can be performed at a higher speed than on an effective screen. The goal is to provide equipment.

[Means for solving problems]

The character display device of the present invention includes a character generator ROM that stores a pattern signal of a character to be displayed on a CRT, a display data RAM that stores a code signal of the character, and synchronizes these with a horizontal synchronization signal and a vertical synchronization signal. an oscillation circuit that outputs a control signal, a vertical address counter, a horizontal address counter, and the data RA that outputs data to be displayed in synchronization with the horizontal synchronization signal.
A character display device consisting of a microcomputer that writes to M is provided with means for causing a horizontal synchronization signal to pass through which write synchronization circuit only during the vertical retrace period.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a CRT character display device showing one embodiment of the present invention, and FIG. 2 is a timing chart of a write enable signal to the display data RAM in FIG. 1.

In the figure, a horizontal address counter 2 counts dot clock signals output from an oscillation circuit 1 and outputs a digit selection signal. Note that this digit selection signal is reset by the horizontal synchronization signal. Similarly, vertical address counter 3
counts vertical synchronization signals and outputs row selection signals.

This row selection signal is reset by the vertical synchronization signal. When the display data RAM 7 outputs a character code signal corresponding to the two row digits selected by the row selection signal and the digit selection signal and inputs it to the character generator ROM 8, the character generator ROM 8 generates a character pattern signal. Character pattern serial output shift register 9 reads this character pattern signal, outputs a character output signal in synchronization with the dot clock signal, and displays it on CTR10.

In order to write display data, the CRT character display device of this embodiment sends input data from the microcomputer 4 to the write address register 5 to write the address (row 9).
As shown in Figure 2, on the valid screen (approximately 52.7 μs) where the vertical synchronizing signal is low level, the invalid signal immediately after the horizontal synchronizing signal is selected via the AND gate 13° write synchronizing circuit 11. The pulse on the screen is used as a write enable signal for the display data RAM 7, and during the blanking period when the vertical synchronization signal is at a high level, the load signal from the microcomputer 4 is directly sent to the display data RAM via the AND gate 12.
Display data is input as the write enable signal of No. 7. That is, use or non-use of the write synchronization circuit 11 is determined by a data selector composed of AND gates 12 and 13 and an inverter 14. Furthermore, switching from the scan address of the display data RAM 7 to the write address is performed by the data selector 6.

Incidentally, as shown in FIG. 2, in the conventional example, the point 1. on the effective screen. When the contents of the display data RAM 21 are rewritten in , flickering occurs on the CR724 screen, but in this embodiment, at time 1. of the invalid screen. Since the contents of the display data RAM 7 are rewritten at the location, there is no effect on the CR710 screen.

〔Effect of the invention〕

As explained above, the present invention uses two AND gates and one
By adding a data selector composed of two inverters, there is an advantage that display data can be sent from the microcomputer at high speed even during the vertical blanking period. Note that since the vertical blanking period is an invalid screen without a video signal, there is no problem such as flickering during writing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a CRT character display device showing an embodiment of the present invention, FIG. 2 is a timing chart of a write enable signal to the display data RAM in FIG. 1, and FIG. 3 is a conventional CTR character display device. It is a block diagram showing an example. 1.15...Oscillation circuit, 2,16...Horizontal address counter, 3.17...Vertical address counter, 4゜18...Microcomputer, 5,19...Write address register, 6,20 ...Data selector, 7.21...
・Display data RAM, 8.22...Character generator ROM, 9.23...Character pattern serial output shift register, 10.24...CRT, 1
1.25...Write synchronization circuit, 12.13...AND gate, 14...Inverter.

Claims (1)

[Claims] A character generator ROM that stores a pattern signal of a character to be displayed on a CRT, a display data RAM that stores a code signal of the character, and a signal that controls these in synchronization with a horizontal synchronization signal and a vertical synchronization signal is output. In a character display device comprising an oscillation circuit, a vertical address counter, a horizontal address counter, and a microcomputer that writes data to be displayed in synchronization with the horizontal synchronization signal into the display data RAM, write synchronization with the horizontal synchronization signal is performed only during the vertical blanking period. A character display device comprising means for bussing a circuit.